Global Ramp Uniformity Correction Method for Super-large Array CMOS Image Sensors
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摘要: 针对大面阵CMOS图像传感器(CIS)中存在的斜坡信号不一致性问题，该文提出一种用于CMOS图像传感器的斜坡一致性校正方法。该误差校正方法基于误差存储和电平移位思想，在列级读出电路中引入用于存储各列斜坡不一致性误差的存储电容，根据存储的斜坡不一致性误差对各列的斜坡信号进行电平移位，确保斜坡信号的一致性。该文基于55 nm 1P4M CMOS工艺对提出的斜坡一致性校正方法完成了详细电路设计和全面仿真验证。在斜坡信号电压范围为1.4 V，斜坡信号斜率为71.908 V/ms，像素面阵规模为8 192(H)×8 192(V),单个像素尺寸为10 μm的设计条件下，该文提出的校正方法将斜坡不一致性误差从7.89 mV降低至36.8 μV。斜坡信号的微分非线性(DNL)为 +0.0013/–0.004 LSB，积分非线性(INL)为+0.045 /–0.02 LSB，列级固定模式噪声(CFPN)从1.9%降低到0.01%。该文提出的斜坡一致性校正方法在保证斜坡信号高线性度，不显著增加芯片面积和不引入额外功耗的基础上，斜坡不一致性误差降低了99.53%，为高精度CMOS图像传感器的设计提供了一定的理论支撑。Abstract: Considering the problem of the non-uniformity of the ramp signal in the large-array CMOS Image Sensors (CIS), a ramp uniformity correction method for CMOS image sensors is proposed in this paper. The correction method is based on error storage and level shift ideas. Storage capacitor that are used to store ramp non-uniformity error are introduced in column readout circuit. According to the stored ramp non-uniformity error, the ramp signal of each column is shifted. So as to ensure the uniformity of the ramp signal. Based on the 55 nm 1P4M CMOS process, this paper has completed the detailed circuit design and comprehensive simulation verification of the proposed method. Under the design conditions that the voltage range of the ramp signal is 1.4 V, the slope of the ramp signal is 71.908 V/ms, the number of pixel area arrays is 8192(H)×8192(V), and a single pixel size is 10 μm, the proposed correction method reduces the ramp non-uniformity error from 7.89mV to 36.8 μV. The Differential NonLinearity (DNL) of the ramp signal is +0.001 3/–0.004 LSB and the Integral NonLinearity (INL) is +0.045/–0.02 LSB. The Column Fixed Pattern Noise(CFPN) is reduced from 1.9% to 0.01%. The proposed ramp uniformity correction method reduces the ramp non-uniformity error by 99.53% on the basis of ensuring the high linearity of the ramp signal, without significantly increasing the chip area and without introducing additional power consumption. It provides a certain theoretical support for the design of high-precision CMOS image sensors.
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