高级搜索

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

低测试逃逸的晶圆级适应性测试方法

梁华国 曲金星 潘宇琦 汤宇新 易茂祥 鲁迎春

梁华国, 曲金星, 潘宇琦, 汤宇新, 易茂祥, 鲁迎春. 低测试逃逸的晶圆级适应性测试方法[J]. 电子与信息学报, 2023, 45(9): 3393-3400. doi: 10.11999/JEIT230852
引用本文: 梁华国, 曲金星, 潘宇琦, 汤宇新, 易茂祥, 鲁迎春. 低测试逃逸的晶圆级适应性测试方法[J]. 电子与信息学报, 2023, 45(9): 3393-3400. doi: 10.11999/JEIT230852
LIANG Huaguo, QU Jinxing, PAN Yuqi, TANG Yuxin, YI Maoxiang, LU Yingchun. Wafer-Level Adaptive Testing Method with Low Test Escape[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3393-3400. doi: 10.11999/JEIT230852
Citation: LIANG Huaguo, QU Jinxing, PAN Yuqi, TANG Yuxin, YI Maoxiang, LU Yingchun. Wafer-Level Adaptive Testing Method with Low Test Escape[J]. Journal of Electronics & Information Technology, 2023, 45(9): 3393-3400. doi: 10.11999/JEIT230852

低测试逃逸的晶圆级适应性测试方法

doi: 10.11999/JEIT230852
基金项目: 国家重大科研仪器研制项目(62027815),国家自然科学基金重点项目(61834006)
详细信息
    作者简介:

    梁华国:男,教授,研究方向为容错计算与硬件安全

    曲金星:男,硕士生,研究方向为集成电路测试

    潘宇琦:男,博士生,研究方向为集成电路测试

    汤宇新:男,硕士,研究方向为集成电路测试

    易茂祥:男,教授,研究方向为VLSI可靠性及安全性设计

    鲁迎春:男,副教授,研究方向为集成电路硬件安全

    通讯作者:

    梁华国 huagulg@hfut.edu.cn

  • 中图分类号: TN407

Wafer-Level Adaptive Testing Method with Low Test Escape

Funds: The National Major Research Instrument Development Project (62027815), The National Natural Science Foundation of China Key Project (61834006)
  • 摘要: 为了降低集成电路中测试成本,提高测试质量,该文提出一种低测试逃逸率的晶圆级适应性测试方法。该方法根据历史测试数据中测试项检测故障晶粒的有效性筛选测试集,降低待测晶圆的测试成本。同时,分析晶粒邻域参数波动程度,将存在波动晶粒的参数差异进行放大并建模,提高该类晶粒质量预测模型的分类准确率;无波动的晶粒使用有效测试集建模的方法进行质量预测,减少测试逃逸的风险。根据实际晶圆生产数据的实验结果表明,该方法可以明显降低晶圆的测试项成本40.13%,并保持较低的测试逃逸率0.0091%。
  • 图  1  工艺波动影响参数均值差异图

    图  2  邻域参数波动图

    图  3  随机森林建模过程

    图  4  基于低测试逃逸的晶圆级适应性测试方法建模流程

    图  5  有效测试集筛选流程

    图  6  晶粒$ t $的邻域晶粒分布

    图  7  晶粒邻域参数波动

    图  8  参数差异放大前后数值对比

    图  9  参数差异放大前后建模测试逃逸数量对比

    图  10  参数差异放大前后建模产量损失数量对比

    表  1  实验数据分布

    批次晶粒总数平均良率(%)测试项数
    138364098.5567
    231231298.9639
    378927699.7625
    下载: 导出CSV

    表  2  对比实验结果(%)

    方案TIRRTERYLR
    本文方法40.130.00910.0137
    方法145.230.05700.0337
    方法235.850.01880.0274
    下载: 导出CSV
  • [1] LIU Mengyun, PAN Renjian, YE Fangming, et al. Fine-grained adaptive testing based on quality prediction[J]. ACM Transactions on Design Automation of Electronic Systems, 2020, 25(5): 38. doi: 10.1145/3385261
    [2] YILMAZ E, OZEV S, SINANOGLU O, et al. Adaptive testing: Conquering process variations[C]. 2012 17th IEEE European Test Symposium, Annecy, France, 2012: 1–6.
    [3] WANG Rui, ZHANG Linmiao, and CHEN Nan. Spatial correlated data monitoring in semiconductor manufacturing using gaussian process model[J]. IEEE Transactions on Semiconductor Manufacturing, 2019, 32(1): 104–111. doi: 10.1109/TSM.2018.2883763
    [4] XUE Cheng and SHAWN R D. A one-pass test-selection method for maximizing test coverage[C]. 2015 33rd IEEE International Conference on Computer Design, New York, USA, 2015: 621–628.
    [5] PAN Renjian, ZHANG Zhaobo, LI Xin, et al. Black-box test-cost reduction based on Bayesian network models[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40(2): 386–399. doi: 10.1109/TCAD.2020.2994257
    [6] LIU Mengyun, LI Xin, CHAKRABARTY K, et al. Knowledge transfer in board-level functional fault diagnosis enabled by domain adaptation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, 41(3): 762–775. doi: 10.1109/TCAD.2021.3065919
    [7] XU Hongwei, ZHANG Jie, LV Youlong, et al. Hybrid feature selection for wafer acceptance test parameters in semiconductor manufacturing[J]. IEEE Access, 2020, 8: 17320–17330. doi: 10.1109/ACCESS.2020.2966520
    [8] LIN Fan, HSU C K, and CHENG K T. AdaTest: An efficient statistical test framework for test escape screening[C]. 2015 IEEE International Test Conference, Anaheim, USA, 2015: 1–8.
    [9] LIN Fan, HSU C K, and CHENG K T. Learning from production test data: Correlation exploration and feature engineering[C]. 2014 IEEE 23rd Asian Test Symposium, Hangzhou, China, 2014: 236–241.
    [10] LIN Fan, HSU C K, and CHENG K T. Feature engineering with canonical analysis for effective statistical tests screening test escapes[C]. 2014 International Test Conference, Seattle, USA, 2014: 1–10.
    [11] SHINTANI M, MIAN R U H, INOUE M, et al. Wafer-level variation modeling for multi-site RF IC testing via hierarchical Gaussian process[C]. 2021 IEEE International Test Conference, Anaheim, USA, 2021: 103–112.
    [12] ZHANG Jinli, YOU Hailong, JIA Renxu, et al. The research on screening method to reduce chip test escapes by using multi-correlation analysis of parameters[J]. IEEE Transactions on Semiconductor Manufacturing, 2022, 35(2): 266–271. doi: 10.1109/TSM.2022.3144283
    [13] KATRAGADDA V, MUTHEE M, GASASIRA A, et al. Algorithm based adaptive parametric testing for outlier detection and test time reduction[C]. 2018 IEEE International Conference on Microelectronic Test Structures, Austin, USA, 2018: 142–146.
    [14] KUO Y T, LIN Weichen, CHEN Chun, et al. Minimum operating voltage prediction in production test using accumulative learning[C]. 2021 IEEE International Test Conference, Anaheim, USA, 2021: 47–52.
    [15] DAASCH W R, COTA K, MCNAMES J, et al. Neighbor selection for variance reduction in I/sub DDQ/ and other parametric data[C]. The International Test Conference, Baltimore, USA, 2002: 1240–1248.
    [16] ZHANG Jinli, YOU Hailong, and JIA Renxu. Reliability hazard characterization of wafer-level spatial metrology parameters based on LOF-KNN method[C]. 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits, Hangzhou, China, 2019: 1–4.
    [17] YANG Chenghao, YEN C H, WANG Tingrui, et al. Identifying good-dice-in-bad-neighborhoods using artificial neural networks[C]. 2021 IEEE 39th VLSI Test Symposium, San Diego, USA, 2021: 1–7.
  • 加载中
图(10) / 表(2)
计量
  • 文章访问数:  303
  • HTML全文浏览量:  182
  • PDF下载量:  34
  • 被引次数: 0
出版历程
  • 收稿日期:  2023-08-04
  • 修回日期:  2023-08-18
  • 录用日期:  2023-08-21
  • 网络出版日期:  2023-08-23
  • 刊出日期:  2023-09-27

目录

    /

    返回文章
    返回