基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计

惠亚娟; 李青朕; 王雷敏; 刘成

doi:10.11999/JEIT230815

基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计

doi: 10.11999/JEIT230815

惠亚娟^{1, 2, 3, ,},
李青朕^{1, 2, 3},
王雷敏^{1, 2, 3},
刘成⁴

1.
中国地质大学(武汉)自动化学院武汉 430074
2.
复杂系统先进控制与智能自动化湖北省重点实验室武汉 430074
3.
地球探测智能化技术教育部工程研究中心武汉 430074
4.
中国科学院计算技术研究所北京 100080

基金项目: 国家自然科学基金 (62104217)

详细信息

作者简介:
惠亚娟：女，副教授，研究方向为自旋器件及存储计算融合电路设计

李青朕：男，硕士生，研究方向为自旋器件及存储计算融合电路设计

王雷敏：男，教授，研究方向为忆阻电路设计及忆阻神经网络应用

刘成：男，副研究员，研究方向为计算机体系结构，容错计算

通讯作者:
惠亚娟　huiyj@cug.edu.cn

中图分类号: TN43
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- 被引次数: 0
出版历程
- 收稿日期: 2023-08-01
- 修回日期: 2023-11-26
- 网络出版日期: 2023-11-29
- 刊出日期: 2024-06-30

In-memory Wallace Tree Multipliers Based on Majority Gates with Voltage Gated Spin-Orbit Torque Magnetoresistive Random Access Memory Devices

HUI Yajuan^{1, 2, 3
, ,},
LI Qingzhen^{1, 2, 3},
WANG Leimin^{1, 2, 3},
LIU Cheng⁴

1.
Institute of Automation, China University of Geoscience(Wuhan), Wuhan 430074, China
2.
Key Laboratory of Advanced Control and Intelligent Automation for Complex Systems, Wuhan 430074, China
3.
Engineering Research Center of Intelligent Technology for Geo-Exploration, Ministry of Education, Wuhan 430074, China
4.
Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China

Funds: The National Natural Science Foundation of China (62104217)

摘要

摘要: 在使用新型非易失性存储阵列进行存内计算的研究中，存内乘法器的延迟往往随着位宽的增加呈指数增长，严重影响计算性能。该文设计一种电压调控自旋轨道矩磁随机存储器(VGSOT-MRAM)单元交叉阵列，并提出一种存内华莱士树乘法器的电路设计方法。所提串联存储单元结构通过电阻求和的方式，有效解决磁存储器单元阻值较低的问题；其次提出基于电压调控自旋轨道矩磁存储器单元交叉阵列的存内计算架构，利用在“读”操作期间实现的5输入多数决定逻辑门，进一步降低华莱士树乘法器的逻辑深度。与现有乘法器设计方法相比，所提方法延迟开销从O(n²)降低为O(log₂ n)，在大位宽时延迟更低。
- 存算一体 /
- 新型非易失性存储器 /
- 自旋轨道矩磁存储器 /
- 华莱士树乘法器
Abstract: In the research on utilizing emerging non-volatile storage arrays for in-memory computing, the latency of in-memory multipliers often exhibits exponential growth with increasing bit width, and significantly impacts the computational performance. A Voltage-Gated Spin-Orbit Torque Magnetoresistive Random-Acess Memory (VGSOT-MRAM) device unit crossbar array is proposed and a circuit design approach for in-memory Wallace tree multipliers is presented in this paper. The proposed series-connected storage unit structure effectively addresses the issue of low resistance values in magnetic storage units through resistive summing. Furthermore, an in-memory computing architecture based on a voltage-controlled spin-orbit torque magnetic storage unit crossbar array is introduced. Finally, a five-input majority decision logic gate implemented during the “read” operation is leveraged to further reduce the logic depth of the Wallace tree multiplier. Compared to existing multiplier design methods, the proposed approach reduces the delay overhead from O(n²) to O(log₂ n), with even lower latency for larger bit widths.
- Processing in memory /
- New non-volatile memory /
- Spin-Orbit Torque Magnetoresistive Random-Acess Memory (SOT-MRAM) /
- Wallace tree multiplier

HTML全文

图 1 电压调控SOT 器件结构示意图

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图 2 VG-SOT MTJ在I_SOT与V_g共同作用下的切换情况

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图 3 基于电压调控SOT器件的交叉阵列

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图 4 基于电压调控SOT器件的5输入多数决定逻辑门电路示意图

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图 5 基于电压调控SOT器件交叉阵列的存内计算系统架构

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图 6 4 × 4华莱士树乘法器运算原理

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图 7 4 × 4华莱士树乘法器运算到存储单元的映射规则

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图 8 输入为A = 1011和B = 1101时，基于电压调控SOT器件多数决定逻辑门的存内华莱士树乘法器仿真结果

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图 9 电压调控SOT-MRAM的版图布局

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图 10 不同类型的乘法器的延迟随乘数位宽增加的变化对比

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图 11 5输入与3输入多数决定逻辑门构成全加器的映射对比

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表 1 电压调控SOT磁隧道结模型参数

参数	名称	数值
t_f	自由层厚度(nm)	1.1
t_o	MgO层厚度(nm)	1.4
TMR	在无偏置电压时TMR比(%)	100%
d, l, w	AFM的厚度、长度、宽度(nm)	3, 50, 60
D	MTJ的直径(nm)	50
ρ_ch	电阻率(μ$ \Omega $·cm)	160
θ_SHE	自旋霍尔角	0.25
R·A	电阻与面积乘积($ \Omega $·μm²)	650
H_ex	交换偏置(Oe)	–180
β	VCMA参数(fJ/V·M)	60

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表 2 不同类型的乘法器计算延迟(cycles)和单元占用单元数量对比

文献	4 × 4		n × n
文献	机器周期	占用单元	机器周期	占用单元
[26]	195	200	15n² – 11n – 1	15n² – 9n – 1
[27]	158	75	13n² – 14n + 6	20n – 5
[10]	139	49	n log₂ n + 14n + 3	14n – 7
[9]	102	38	(log₂ n) (10n + 2) + 4n + 2	2n² + n + 2
[11]	32	128	6 log₂ (n²/4) + 4 [log₂ 2(n – log₂ n)] + (n – 2) (log₂ n – 2)+ 10	8n² + 48 log₂ (n/4)
本文	28	112	5 log₂ (n²/4) + 4 log₂ [2(n – log₂ n)] + 10	7n² + 42 log₂ (n/4)

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