面向CMOS图像传感器芯片的3D 芯粒(Chiplet) 非接触互联技术

徐志航; 徐永烨; 马同川; 杜力; 杜源

doi:10.11999/JEIT230382

面向CMOS图像传感器芯片的3D 芯粒(Chiplet) 非接触互联技术

doi: 10.11999/JEIT230382

南京大学电子科学与工程学院南京 210023

基金项目: 国家重点研发计划(2021YFA0717700)，国家自然科学基金(62211530492, 62004096)

详细信息

作者简介:
徐志航：男，博士生，研究方向为模拟集成电路

徐永烨：男，硕士生，研究方向为模拟集成电路

马同川：男，博士生，研究方向为射频微波集成电路

杜力：男，副教授，研究方向为模拟与人工智能计算芯片

杜源：男，副教授，研究方向为高速互联与异构计算芯片

通讯作者:
杜源　yuandu@nju.edu.cn

中图分类号: TN403; TN43
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- 被引次数: 0
出版历程
- 收稿日期: 2023-05-06
- 修回日期: 2023-08-19
- 录用日期: 2023-08-21
- 网络出版日期: 2023-08-23
- 刊出日期: 2023-09-27

3D Contactless Chiplet Interconnects for CMOS Image Sensor

School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China

Funds: The National Key Research and Development Program of China (2021YFA0717700), The National Natural Science Foundation of China (62211530492, 62004096)

摘要

摘要: 在后摩尔时代，3D芯粒(Chiplet)通常利用硅通孔(TSV)进行异构集成，其复杂的工艺流程会提高芯片制造的难度和成本。针对背照式(BSI)CMOS图像传感器(CIS)的倒置封装结构，该文提出了一种低成本、低工艺复杂度的3D Chiplet非接触互联技术，利用电感耦合构建了数据源、载波源和接收机3层分布式收发机结构。基于华润上华(CSMC)0.25 μm CMOS工艺和东部高科(DB HiTek)0.11 μm CIS工艺，通过仿真和流片测试验证了所提出的互联技术的有效性。测试结果表明，该3D Chiplet非接触互联链路采用20 GHz载波频率，收发机通信距离为5～20 μm，在数据速率达到200 Mbit/s时，误码率小于10^–8，接收端功耗为1.09 mW，能效为5.45 pJ/bit。
- 芯粒(Chiplet) /
- 电感耦合 /
- 3维芯片集成技术 /
- CMOS图像传感器
Abstract: In the post-Moore era, 3D Chiplet clusters are typically integrated heterogeneously using Through Silicon Vias (TSVs), whose complex flow increases the difficulty and cost of chip manufacturing. Based on the upside-down packaging of BackSide-Illuminated (BSI) CMOS Image Sensors (CIS), a 3D Chiplet non-contact interconnection technique with low-cost and low packaging complexity is proposed. Using inductive coupling, a three-layer distributed transceiver structure of data source, carrier source, and receiver is constructed. Based on CSMC 0.25 μm CMOS process and DB-HiTek 0.11 μm CIS process, the feasibility of the proposed interconnects is verified by simulation and chip measurement. The test results show that the 3D Chiplet non-contact link can cover 5～20 μm communication distance with 20 GHz carrier frequency, achieving a BER of less than 10^-8 at the data rate of 200 Mbit/s. The power consumption of the receiver is 1.09 mW, and the energy efficiency of it is 5.45 pJ/bit.
- Chiplet /
- Inductive coupling /
- 3D integrated interconnects /
- CMOS Image Sensor (CIS)

HTML全文

图 1 面向CIS芯粒与数字芯粒间互联的3D Chiplet 非接触高速互联

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图 2 HFSS耦合电感的电磁仿真建模

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图 3 信道损耗的影响因素

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图 4 同层电感阵列串扰分析

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图 5 3D Chiplet 非接触链路系统结构

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图 6 联合仿真时域结果

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图 7 测试环境和芯片引线键合的显微照片

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图 8 测试平台与眼图

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