NN-EdgeBuilder: High-performance Neural Network Inference Framework for Edge Devices
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摘要: 飞速发展的神经网络已经在目标检测等领域取得了巨大的成功，通过神经网络推理框架将网络模型高效地自动部署在各类边缘端设备上是目前重要的研究方向。针对以上问题，该文设计一个针对边缘端FPGA的神经网络推理框架NN-EdgeBuilder，能够利用基于多目标贝叶斯优化的设计空间探索算法充分探索网络每层的并行度因子和量化位宽，接着调用高性能且通用的硬件加速算子来生成低延迟、低功耗的神经网络加速器。该文使用NN-EdgeBuilder在Ultra96-V2 FPGA上部署了UltraNet和VGG网络，生成的UltraNet-P1加速器与最先进的UltraNet定制加速器相比，功耗和能效比表现分别提升了17.71%和21.54%。与主流的推理框架相比，NN-EdgeBuilder生成的VGG加速器能效比提升了4.40倍，数字信号处理器(DSP)的计算效率提升了50.65%。Abstract: The rapidly developing neural network has achieved great success in fields such as target detection. Currently, an important research direction is to deploy efficiently and automatically network models on various edge devices through a neural network inference framework. In response to these issues, a neural network inference framework NN-EdgeBuilder for edge FPGA is designed in this paper, which can fully explore the parallelism factors and quantization bit widths of each layer of the network through a design space exploration algorithm based on multi-objective Bayesian optimization. Then high-performance and universal hardware acceleration operators are called to generate low-latency and low-power neural network accelerators. NN-EdgeBuilder is used to deploy UltraNet and VGG networks on Ultra96-V2 FPGA in this study, and the generated UltraNet-P1 accelerator improves power consumption and energy efficiency by 17.71% and 21.54%, respectively, compared with the state-of-the-art UltraNet custom accelerator. Compared with mainstream inference frameworks, energy efficiency of the VGG accelerator generated by NN-EdgeBuilder is improved by 4.40 times and Digital Signal Processor(DSP) computing efficiency is improved by 50.65%.
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算法1 全连接运算循环嵌套 (1) Loop1: $ \text{ for(ci=0;ci < CI;ci++)} $ (2) Loop2: $ \text{ for(co=0;co < CO;co++)} $ (3) ${ {\boldsymbol{O} }_{{\rm{fc}}} }[{\rm{co}}]$+=$ {I_{{\text{fc}}}}{\text{[ci]}} \times {F_{{\text{fc}}}}{\text{[co,ci]}} $ (4) EndLoop 
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算法2 卷积运算循环嵌套 (1) Loop1: $ \text{ for(wo=0;wo < WO;wo++)} $ (2) Loop2: $ \text{ for(ho=0;ho < HO;ho++)} $ (3) Loop3: $ \text{ for(co=0;co < CO;co++)} $ (4) Loop4: $ \text{ for(ci=0;ci < CI;ci++)} $ (5) Loop5: $ \text{ for(hf=0;hf < HF;hf++)} $ (6) Loop6: $ \text{ for(wf=0;wf < WF;wf++)} $ (7) ${ {\boldsymbol{O} } }_{\text{conv} }[{\rm{co}},{\rm{ho}},{\rm{wo}}]$+=${I_{ {\text{conv} } } }[{\rm{ci}},{\rm{ho} } + {\rm{hf} },$
${\rm{wo}} + {\rm{wf}}] \times{F_{ {\text{conv} } } }{\text{[co,ci,hf,wf]} }$(8) EndLoop
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算法3 贝叶斯优化算法流程 输入：设计空间$F$，代理模型${ {\rm{GP}} _M}$，采集函数${{\rm{EHVIC}}}$，目标
函数${\varphi }(x)$，约束$ {C}(x) $输出：推理框架NN-EdgeBuilder自动部署的加速器设计空间的
Pareto前沿$P({{\mathcal{V} } })$(1) 在$F$内采样，得到包含$J$个样本的数据集${D_{\varphi } } = ({\boldsymbol{X}},{\boldsymbol{Y}})$，约
束集${D_{C}} = \{ {C}(x)\} $(2) while !(停止条件) do (3) 根据样本集${D_{\varphi }}$和约束集${D_{C}}$拟合代理模型${ {\rm GP} _{{M} } }$ (4) 对于$ \forall p \in {P_n} $，算出期望的超体积改进量${{\rm{EHVI}}} (x)$和满足
约束的期望${{\rm{CS}}} (p)$(5) 求出采集函数的极值${x^{J + 1} } = \arg \mathop {\max }\limits_{x \in F} {{\rm{EHVIC}}} (x)$，选择
新的采样点(6) 运行Vivado工具流得到准确的函数值${\varphi }({x^{J + 1}})$，约束
$ {C}({x^{J + 1}}) $(7) 更新数据集${D_{\varphi }}$和约束集${D_{C}}$ (8) end while (9) return加速器设计空间的Pareto前沿$ P({ {\mathcal{V} } }) $
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表 1 UltraNet加速器性能对比
加速器 IOU FPS Energy(J) GOPS GOPS/W UltraNet-P1 0.702 2107 30.2 387.7 319.9 UltraNet-P2 0.703 2090 33.0 384.6 292.8 SEUer 0.703 2020 36.7 371.7 263.2 ultrateam 0.703 2266 40.3 416.9 239.7
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表 2 NN-EdgeBuilder和其他推理框架部署VGG网络的性能对比
NN-EdgeBuilder DeepBurning-SEG[6] fpgaConvNet[7] HyBridDNN[8] DNNBuilder[9] 支持的
深度学习框架PyTorch,
TensorFlow & Keras– Caffe & Torch – Caffe FPGA平台 ZU3EG ZU3EG XC7Z020 XC7Z020 XC7Z045 频率(MHz) 250 200 125 100 200 DSP 360 264 220 220 680 量化精度 4 bit 8 bit 16 bit 16 bit 8 bit GOPS 418 203 48 83 524 GOPS/DSP 1.16 0.77 0.22 0.38 0.77 GOPS/W 320.2 – 7.3 32.0 72.8
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