基于图神经网络的电子设计自动化技术研究进展

田春生; 陈雷; 王源; 王硕; 周婧; 王卓立; 庞永江; 杜忠

doi:10.11999/JEIT230266

基于图神经网络的电子设计自动化技术研究进展

doi: 10.11999/JEIT230266

田春生^1, ,,
陈雷¹,
王源²,
王硕¹,
周婧¹,
王卓立¹,
庞永江¹,
杜忠¹

1.
北京微电子技术研究所北京 100076
2.
北京大学集成电路学院北京 100871

基金项目: 国家自然科学基金(U20A20204)，国家重大科技专项(2009ZYHJ0005)

详细信息

作者简介:
田春生：男，博士，研究方向为集成电路自动化设计

陈雷：男，研究员，研究方向为FPGA, Soc, ASIC等VLSI研发

王源：男，教授，研究方向为大规模集成电路设计

王硕：男，硕士，研究方向为FPGA CAD算法

周婧：女，硕士，研究方向为故障注入、刷新技术、单粒子效应缓解技术

王卓立：男，硕士生，研究方向为逻辑综合、单粒子效应软件缓解技术

庞永江：男，硕士，研究方向为软件应用、 IDE设计

杜忠：男，研究员，研究方向为软件应用、抗辐照技术、FPGA测试、FPGA EDA

通讯作者:
田春生　tiancs@pku.edu.cn

中图分类号: TN47; TP301
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出版历程
- 收稿日期: 2023-04-12
- 修回日期: 2023-07-12
- 网络出版日期: 2023-07-18
- 刊出日期: 2023-09-27

A Survey for Electronic Design Automation Based on Graph Neural Network

1.
Beijing Microelectronics Technology Institute, Beijing 100076, China
2.
School of Integrated Circuits, Peking University, Beijing 100871, China

Funds: The National Natural Science Foundation of China (U20A20204), The National Key S&T Special Projects (2009ZYHJ0005)

摘要

摘要: 在摩尔定律的推动下，工艺节点在不断演进，集成电路设计复杂度也在不断增加，电子设计自动化(EDA)技术面临着来自运行时间与计算资源等诸多方面的挑战。为了缓解这些挑战，机器学习方法已被纳入EDA工具的设计流程中。与此同时，鉴于电路网表作为图形数据的本质，图神经网络(GNN)在EDA流程中的应用正变得越来越普遍，为复杂问题的建模以及最优问题的求解带来了新思路。该文首先对GNN与EDA技术的概念内涵进行了简要的概述，详细地梳理了GNN在高层次综合(HLS)、逻辑综合、布图规划与布局、布线、反向工程、硬件木马检测以及测试点插入等不同EDA设计流程中的主要作用，以及当前基于GNN的EDA技术的一些重要探索。以希望为集成电路设计自动化以及相关领域的研究人员提供参考，为我国先进集成电路产业的发展提供技术支持。
- 电子设计自动化 /
- 图神经网络 /
- 先进集成电路技术 /
- 敏捷设计
Abstract: Driven by Moore’s law, the aggressive shrinking of feature sizes, and the complexity of the chip design is also steadily increasing. Electronic Design Automation (EDA) technology faces challenges from many aspects such as runtime and computing resources. To alleviate these challenges, machine learning methods are incorporated into the design process of EDA tools. At the same time, given the nature of circuit netlist as graphical data, the application of Graph Neural Network (GNN) in the EDA is becoming more and more common, bring new ideas for modeling complex problems and solving optimal problems. A brief overview of the concept GNN and EDA is presented. The main role of GNN in different EDA stages such as High Level Synthesis (HLS), logic synthesis, floorplan and placement, routing, reverse engineering, hardware trojan detection and test point insertion is summarized. The main role of GNN in the EDA design process is sorted out in detail, as well as some important explorations of current GNN-based EDA technology. It is hoped to provide reference for researchers in integrated circuit design automation and related fields, and provide technical support for China’s advanced integrated circuit industry.
- Electronic Design Automation (EDA) /
- Graph Neural Network (GNN) /
- Advanced integrated circuit technology /
- Agile design

HTML全文

图 1 两种数据结构

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图 2 EDA设计流程

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图 3 算术密集型设计中基于GNN的运算映射与聚类学习

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图 4 IRONMAN体系架构示意图

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图 5 HLS性能预测方法体系架构示意图

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图 6 基于GraphSAGE的短路违例预测方法

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图 7 基于GNN的子电路提取与分类方法示意图

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表 1 基于GNN的EDA技术

EDA技术分类	GNN模型	具体描述	参考文献
逻辑综合	GraphSAGE	HLS阶段学习如何将算术运算映射为实际的FPGA资源	文献[26]: D-SAGE
	GCN	在尽可能早的阶段快速完成对HLS设计关于资源使用和时序性能的预测评估	文献[27]
	GCN	HLS阶段进行性能的预测评估，同时进行设计空间探索，提供不同目标间的帕累托最优解决方案	文献[28]: IRONMAN 文献[29]: IRONMAN-PRO
	GCN	利用来自硬件设计和逻辑综合流程的空时信息完成不同设计在各种逻辑综合流程中关于延时及面积信息的预测	文献[30]: LOSTIN
布图规划与布局	Edge-GNN 图强化学习	将数字集成电路宏模块布图规划问题转化为强化学习问题，进一步进行求解	文献[31]
	GraphSAGE	将逻辑单元进行聚类，从而优化布局流程，加速布局流程收敛	文献[32]、文献[33]
	GCN	同时考虑了宏模块与标准单元的布局求解问题	文献[34]: DeepPlace
	GCN	布局阶段完成拥塞预测	文献[35]
	GCN	布局阶段完成拥塞预测	文献[36]
	GraphSAGE	通过提取完整的能够反映短路违例的特征参数，在布局阶段利用GraphSAGE模型完成短路违例的预测	文献[37]
布线	GCN	利用GCN的详细节点嵌入作为强化学习的策略网络指导布线流程的优化	文献[34]: DeepPR
反向工程与硬件木马检测	GAT/GraphSAINT	门级网表中进行子电路的分类与提取	文献[43]: GNN-RE
	ABGNN	提升GNN在门级网表算数块识别过程中的可扩展性，并利用开源RISC-V处理器的门级网表进行验证	文献[44]
	GCN	在事先不了解设计IP或硬件木马结构的前提下完成对RTL设计中硬件木马的快速检测与识别	文献[45]: GNN4TJ 文献[46-49]
测试点的选取	GCN	快速进行测试点的插入以及时序模型的选择	文献[20]
测试点的选取	GCNNs	快速处理数字逻辑电路中不规则的图表示，提高故障覆盖率	文献[51]

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参考文献(53)

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