High-speed Fully Differential Two-step ADC Design Method for CMOS Image Sensor
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摘要: 由于传统的单斜式模数转换器(SS ADC)以及改进的各种架构串行两步式SS ADC普遍存在速度瓶颈问题，均无法满足工业界高帧率CMOS图像传感器的发展需求，该文提出一种应用于高帧率CMOS图像传感器的高速全差分两步式ADC设计方法。该ADC设计方法基于差动斜坡与时间数字转换(TDC)技术，将差动量化嵌套在两步式的量化中，形成了区别于串行量化的并行量化模式，不仅提升了数据量化的速率，而且保证了系统的一致性和鲁棒性；针对传统TDC技术与单斜式ADC的匹配性问题，提出了一种基于电平编码的TDC技术，在ADC量化的最后一个时钟周期内，在不提升系统时钟的情况下，完成时间数字转换，实现了更高精度的量化。该文基于55 nm 1P4M CMOS实验平台完成了所提方法的电路设计、版图设计和测试验证。在模拟电压3.3 V、数字电压1.2 V、时钟频率100 MHz、动态输入范围1.6 V的设计环境下，该文ADC设计精度为12 bit，转换时间仅有480 ns，列级功耗低至62 μW，DNL以最低有效位(LSB)计为+0.6/–0.6，INL以最低有效位(LSB)计为+1.2/–1.4，信噪失真比(SNDR)达到70.08 dB，与现有的先进单斜式ADC相比，ADC转换速度提高了52%以上，可以有效压缩行处理时间，为高帧率大面阵CMOS图像传感器的实现提供了有效的解决方案。Abstract: Due to the common speed bottleneck problem of traditional Single-Slope Analog-to-Digital Converter (SS ADC) and serial two-step ADC, the application requirements of high frame rate CMOS Image Sensor (CIS) in the industry have not been met. In this paper, a high-speed fully differential two-step ADC design method for CIS is proposed. The ADC design method is based on differential ramp and Time-to-Digital Conversion (TDC) technology. A parallel conversion mode is formed, which is different from serial conversion, and the robustness of the system is ensured due to the existence of differential ramps. Focusing on the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding is proposed, which completes time-to-digital conversion in the last clock cycle of A/D conversion, and realizes a two-step conversion process at another level. Based on the 55 nm 1P4M CMOS experimental platform, this paper completes the circuit design, layout design and test verification of the proposed design method. Under the design environment of analog voltage 3.3 V, digital voltage 1.2 V, clock frequency 100MHz, and dynamic input range 1.6 V, this design is a 12 bit ADC, the conversion time is 480 ns, the column-level power consumption is 62 μW, the DNL (Differential Non-Linearity is measured in the Least Significant Bit) is +0.6/–0.6, the INL (Integral Non-Linearity is measured in the Least Significant Bit) is +1.2/–1.4, and the Signal-to-Noise Distortion Ratio (SNDR) reaches 70.08 dB. Compared with the existing advanced single-slope ADC, the ADC conversion speed is increased by more than 52%, which is a large area array with high frame rate. It provides an effective solution for the implementation of high frame frequency CIS.
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Key words:
- CMOS Image Sensor(CIS) /
- Differential ramp /
- Time-to-Digital Conversion(TDC) /
- Level encoding /
- Two-step
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表 1 本文设计方法与文献的对比结果
文献[22] 文献[23] 文献[24] 文献[1] 本文 工艺(nm) 130 – 55 130 55 结构 两步式 两步式 全并行两步式 单斜式+TDC 全差分两步式+TDC ADC 精度(bit) 12 12 12 12 12 量化范围(V) 1.2 – 1.472 – 1.6 转换时间 10 μs 6.38 μs 1.28 μs 1 μs 480 ns DNL 0.76/–0.8 +1.34/–0.49 +0.8/–0.8 +1.1/–0.4 +0.6/–0.6 INL 1.06/–0.84 +2.44/–2.47 +2.1/–3.5 +5.8/–8.2 +1.2/–1.4 有效位数(bit) 11.25 – 11.33 – 11.35 功耗(μW) 72 112.5 47 177 62 品质因数*( pJ/conv.-step) 0.296 0.175 0.023 0.043 0.008 *=功耗/(采样率×2有效位数) 
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