基于ZnO忆阻器的高鲁棒性毛刺型物理不可克隆函数设计

陈鑫辉; 倪力; 刘子坚; 张跃军; 陈祺来; 刘钢

doi:10.11999/JEIT221086

基于ZnO忆阻器的高鲁棒性毛刺型物理不可克隆函数设计

doi: 10.11999/JEIT221086

1.
金华职业技术学院信息工程学院金华 321017
2.
宁波大学信息科学与工程学院宁波 315211
3.
上海交通大学电子信息与电气工程学院上海 200240

基金项目: 国家自然科学基金(61871244, 62104267)，浙江省省属高校基本科研业务费专项资金(SJLY2020015)，浙江省大学生新苗人才计划(2022R474A001)，金华市重大(重点)科学技术研究计划(2021-1-014)

详细信息

作者简介:
陈鑫辉：男，助教，研究方向为忆阻器电路设计及实现

倪力：男，硕士生，研究方向为安全芯片理论和设计

刘子坚：男，副教授，研究方向为低功耗集成电路设计

张跃军：男，教授，研究方向为低功耗、高信息密度集成电路理论和设计

陈祺来：男，博士后，研究方向为集成电路及新型器件电路设计

刘钢：男，教授，研究方向为基于新型半导体材料的非冯忆阻逻辑器件与神经形态器件

通讯作者:
刘子坚　liuzijian@jhc.edu.cn

中图分类号: TN915.08; TN601
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- 被引次数: 0
出版历程
- 收稿日期: 2022-08-17
- 修回日期: 2022-10-28
- 网络出版日期: 2022-11-05
- 刊出日期: 2023-09-27

Design of Highly Robust Glitch-Physical Uunclonable Functions Based on ZnO Memristor

1.
College of Information Engineering, Jinhua Polytechnic, Jinhua 321017, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
3.
School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China

Funds: The National Natural Science Foundation of China (61871244, 62104267), The Fundamental Research Funds for the Provincial Universities of Zhejiang (SJLY2020015), The Fresh Talent Programme for Science and Technology Department of Zhejiang Province (2022R474A001), The Projects of Major (Key) Science and Technology Research in Jinhua (2021-1-014)

摘要

摘要: 物理不可克隆函数(PUF)作为硬件安全原语，广泛应用于众多领域。针对传统硅基类PUF电路可靠性差和易受建模攻击等问题，该文提出一种基于忆阻器的“毛刺”型物理不可克隆函数电路(Glitch-PUF)。该方案首先利用忆阻器的非易失性和阻变效应，实现二值逻辑完备集；然后，利用完备集和竞争冒险现象设计忆阻毛刺产生模块，通过选通信号控制流经忆阻交叉阵列路径的延时大小，改变“毛刺”宽度获得稳定“毛刺”输出；最后，利用忆阻器的存算一体特性和施密特回滞效应设计忆阻采样模块，并测试Glitch-PUF性能。实验结果表明，所设计的Glitch-PUF电路相比文献，抗攻击性提高4.9%～14.3%，随机性达到98.2%，误码率(BER)为0.08%，具有优异的鲁棒性和稳定性。
- 物理不可克隆函数 /
- 忆阻器 /
- 硬件安全 /
- 稳定性
Abstract: Physical Unclonable Functions(PUF) are widely used in various fields as hardware security primitives. Considering the problems of vulnerability to modeling attacks and low stability of traditional CMOS-based PUF, a memristive Glitch-PUF circuit is proposed in this paper. The non-volatility and resistive effect of memristor are used to achieve the complete set of binary logic circuit. Then, the glitch generation circuit is designed based on the logic complete sets and competition and risk taking phenomenon, the stable glitch is obtained by varying the delay time, which is controlled by the path of the current flowing through crossbar array. Finally, the sampling circuit is designed according to the computing in memory characteristics of the memristor and Schmidt hysteresis effect, and the Glitch-PUF is verified. The experimental results show that the anti-modeling attack of designed Glitch-PUF is improved about 4.9%～14.3%, the randomness reaches 98.2%, and the Bit Error Rate(BER) is 0.08%, showing excellent robustness and stability.
- Physical Unclonable Functions(PUF) /
- Memristor /
- Hardware security /
- Stability

HTML全文

图 1 Pt/ZnO/Pt忆阻器电学参数

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图 2 基于忆阻器的逻辑门

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图 3 毛刺产生原理

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图 4 Glitch PUF电路框图

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图 5 忆阻D触发器模块

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图 6 忆阻毛刺产生模块

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图 7 忆阻采样模块

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图 8 Glitch-PUF电路抗攻击性测试

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图 9 Glitch-PUF电路随机性测试

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图 10 Glitch-PUF电路自相关性测试

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图 11 Glitch-PUF电路唯一性测试

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图 12 Glitch-PUF电路误码率测试

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算法1　忆阻器伪代码程序描述
(1)R_ON=100 R_OFF=5 000 V_ON=0.8 V_OFF=0.8 L₀=3e-9 E_h=0.6 X_T=0.4e-9
(2)f=1e13 I₀=1e13 WCF=5e-9 weff=0.5e-9 R_th= 5e5 E_i=1.45 T₀=300
(3)alpha=0.75e-9 TAU=0.000 1 k=1.380 649e-23 e=1.6e–19 w=0.5e-9
(3)K_b=8.617 33e–5 pi = 3.141 592 6 a=0.25e-9 E_a=0.489 9 rou=1.9e-5
(4)G(v)=V/R_ON+(1–V)/R_OFF
(5)Temp=T₀+abs(I_tb×V_tb×R_th)
(6)dx=–a×f×exp(–(E_a-V_g×alpha×2/x)/(K_b×Temp))
(7)dw=(weff+pow(weff,2)/(2×w))×f×exp(–(E_a–V_tb×alpha×2/L₀)/(K_b×Temp))
(8)I₁=I₀×pi×(WCF×WCF/4-w×w/4)×exp(–L₀/X_T)×sinh(V_tb/V_T)
(9)RCF=rou×(L₀-x)/(pi×w×w/4)
(10)V_g=V_tb–(I_tb–I₁)×RCF
(11)dx/dt =(1/TAU)×((1/(1+exp(–1/(T×k/e)×(V_tb–V_on))))×(1–V_tb)–(1–(1/(1+exp(–1/(T×k/e)×(V_tb+V_off)))))×V₂
(12)IVRel(V₁,V₂)=V₁×G(V₂)

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表 1 NIST测试

测试项目	长度(bit)	测试次数(次)	通过率(%)	P值	测试通过
单比特频数	6400	10	100	0.589	是
块内频数	6400	10	90	0.436	是
累加和	6400	10	100	0.825	是
近似熵	6400	10	100	0.371	是
游程	6400	10	100	0.328	是
最大游程	6400	10	100	0.682	是
离散傅里叶变换	6400	10	100	0.737	是
序列	6400	10	100	0.253	是
通用统计	6400	10	100	0.375	是
二进制矩阵秩	6400	10	100	0.411	是

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表 2 与相关文献的比较结果

比较文献	工艺(nm)	NIST测试	电压(V)	温度(℃)	汉明距离(归一化)	误码率(%)
VLSI^[15]	130	–	1.08～1.3	–20～80	0.499 9	9.000
ISSCC^[16]	65	PASS	0.7～1.0	25～85	0.501 4	1.730
IEDM^[17]	–	PASS	0.8～1.2	25～85	0.499 5	11.500
VLSI^[18]	200	–	1.0～1.3	25～100	0.500 1	5.300
ISSCC^[19]	130	PASS	0.9～1.8	25～125	0.498 9	1.730
TCASI^[20]	65	PASS	0.5～1.0	–10～80	0.494 7	3.000
JSSC^[21]	180	PASS	0.4～1.8	10～80	0.493 0	0.130
本文	65	PASS	0.8～1.4	–20～120	0.500 2	0.008

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参考文献(21)

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