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基于忆阻器的1T1M可重构阵列结构

蒋林 张丁月 李远成 曹非 隆茂森

蒋林, 张丁月, 李远成, 曹非, 隆茂森. 基于忆阻器的1T1M可重构阵列结构[J]. 电子与信息学报, 2023, 45(8): 3047-3056. doi: 10.11999/JEIT220718
引用本文: 蒋林, 张丁月, 李远成, 曹非, 隆茂森. 基于忆阻器的1T1M可重构阵列结构[J]. 电子与信息学报, 2023, 45(8): 3047-3056. doi: 10.11999/JEIT220718
JIANG Lin, ZHANG Dingyue, LI Yuancheng, CAO Fei, LONG Maosen. 1T1M Reconfigurable Array Structure Based on Memristor[J]. Journal of Electronics & Information Technology, 2023, 45(8): 3047-3056. doi: 10.11999/JEIT220718
Citation: JIANG Lin, ZHANG Dingyue, LI Yuancheng, CAO Fei, LONG Maosen. 1T1M Reconfigurable Array Structure Based on Memristor[J]. Journal of Electronics & Information Technology, 2023, 45(8): 3047-3056. doi: 10.11999/JEIT220718

基于忆阻器的1T1M可重构阵列结构

doi: 10.11999/JEIT220718
基金项目: 国家自然科学基金(61834005),陕西省自然科学基金(2020JM-525),榆林市科技计划(CXY-2020-026)
详细信息
    作者简介:

    蒋林:男,教授,研究方向为专用集成电路设计、计算机体系结构

    张丁月:女,硕士生,研究方向为新型非易失性存储器、可重构处理器存储优化

    李远成:男,讲师,研究方向为计算机体系结构

    曹非:男,讲师,研究方向为计算机体系结构

    隆茂森:男,硕士,研究方向为片上光互连

    通讯作者:

    蒋林 jianglin@xust.edu.cn

  • 中图分类号: TN601; TN710; TN79+1

1T1M Reconfigurable Array Structure Based on Memristor

Funds: The National Natural Science Foundation of China (61834005), The Natural Science Foundation of Shaanxi Province (2020JM-525), The Science and Technology Project of Yulin City (CXY-2020-026)
  • 摘要: 忆阻器(Memristor)或者阻变存储器(ReRAM)是一种具有存储和计算功能的新型非易失性存储器(NVM),可以用作存算一体(PIM)的非冯·诺依曼计算机体系架构的基础器件。针对可重构阵列处理器数据计算速度和存储速度不匹配的问题,该文采用电压阈值自适应忆阻器(VTEAM)模型,经过凌力尔特通用模拟电路仿真器(LTSPICE)仿真验证,可以实现布尔逻辑完备集。在此基础上,设计了一种1T1M忆阻器交叉阵列,具有结构简单、可重构性和高并行性的特点,利用蒙特卡罗(MC)法进行容差分析,计算精度达到0.998。该阵列与现有的先进阵列相比,能有效提升芯片的性能,降低处理延迟与能耗,可以与可重构阵列处理器结合以应对“存储墙”问题。
  • 图  1  VTEAM在LTSPICE中的模型子电路

    图  2  VTEAM模型在正弦波激励下的I-V特性

    图  3  MRL与逻辑运算单元

    图  4  MRL或逻辑运算单元

    图  5  MRL非逻辑运算单元

    图  6  MRL逻辑运算仿真曲线

    图  7  电压源MC参数

    图  8  电阻MC参数

    图  9  基于忆阻器的PIM基本电路结构

    图  10  阵列电路

    图  11  4×4阵列

    图  12  外围电路

    图  13  阵列仿真波形

    表  1  忆阻器VTEAM模型参数

    参数βVthRinitRonRoff
    数值e13±0.8 V10 kΩ160 Ω11 kΩ
    下载: 导出CSV

    表  2  NMOS具体参数

    参数VdsRdsQgate
    数值12 V0.003 Ω3.6e-8 C
    下载: 导出CSV

    表  3  逻辑运算单元比较

    设计逻辑单元变量读/写电路延迟(Cycles)
    IMP[19]AND电阻值需要2
    OR电阻值需要3
    NOT电阻值需要1
    MAGIC[21]AND电阻值需要4
    OR电阻值需要2
    NOT电阻值需要1
    FELIX[23]AND电阻值需要2
    OR电阻值需要1
    NOT电阻值需要1
    MRLAND电压值不需要1
    OR电压值不需要1
    NOT电压值不需要1
    下载: 导出CSV

    表  4  1×4阵列、4×1阵列电路性能

    阵列输入值输出值功能
    1×441叠加
    4×141AND
    下载: 导出CSV

    表  5  不同阵列比较情况

    模型存储单元读/写电路延时(ns/bit)功耗(fW/bit)是否重构并行读取
    文献[10]1T2M需要3.0024410.0支持
    文献[11]1T2M需要0.01150.0支持
    文献[12]1TxM需要1.54396.8不支持
    本文1T1M不需要0.01135.7支持
    下载: 导出CSV
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出版历程
  • 收稿日期:  2022-06-01
  • 修回日期:  2022-10-28
  • 网络出版日期:  2022-11-07
  • 刊出日期:  2023-08-21

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