基于忆阻器的1T1M可重构阵列结构

蒋林; 张丁月; 李远成; 曹非; 隆茂森

doi:10.11999/JEIT220718

基于忆阻器的1T1M可重构阵列结构

doi: 10.11999/JEIT220718

1.
西安科技大学计算机科学与技术学院西安 710600
2.
西安科技大学电气与控制工程学院西安 710600
3.
西安科技大学通信与信息工程学院西安 710600

基金项目: 国家自然科学基金(61834005)，陕西省自然科学基金(2020JM-525)，榆林市科技计划(CXY-2020-026)

详细信息

作者简介:
蒋林：男，教授，研究方向为专用集成电路设计、计算机体系结构

张丁月：女，硕士生，研究方向为新型非易失性存储器、可重构处理器存储优化

李远成：男，讲师，研究方向为计算机体系结构

曹非：男，讲师，研究方向为计算机体系结构

隆茂森：男，硕士，研究方向为片上光互连

通讯作者:
蒋林　jianglin@xust.edu.cn

中图分类号: TN601; TN710; TN79+1
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- 被引次数: 0
出版历程
- 收稿日期: 2022-06-01
- 修回日期: 2022-10-28
- 网络出版日期: 2022-11-07
- 刊出日期: 2023-08-21

1T1M Reconfigurable Array Structure Based on Memristor

1.
School of Computer Science and Technology, Xi’an University of Science and Technology, Xi’an 710600, China
2.
School of Electrical and Control Engineering, Xi’an University of Science and Technology, Xi’an 710600, China
3.
School of Communication and Information Engineering, Xi’an University of Science and Technology, Xi’an 710600, China

Funds: The National Natural Science Foundation of China (61834005), The Natural Science Foundation of Shaanxi Province (2020JM-525), The Science and Technology Project of Yulin City (CXY-2020-026)

摘要

摘要: 忆阻器(Memristor)或者阻变存储器(ReRAM)是一种具有存储和计算功能的新型非易失性存储器(NVM)，可以用作存算一体(PIM)的非冯·诺依曼计算机体系架构的基础器件。针对可重构阵列处理器数据计算速度和存储速度不匹配的问题，该文采用电压阈值自适应忆阻器(VTEAM)模型，经过凌力尔特通用模拟电路仿真器(LTSPICE)仿真验证，可以实现布尔逻辑完备集。在此基础上，设计了一种1T1M忆阻器交叉阵列，具有结构简单、可重构性和高并行性的特点，利用蒙特卡罗(MC)法进行容差分析，计算精度达到0.998。该阵列与现有的先进阵列相比，能有效提升芯片的性能，降低处理延迟与能耗，可以与可重构阵列处理器结合以应对“存储墙”问题。
- 存算一体 /
- 忆阻器 /
- 阵列 /
- 可重构
Abstract: Memristor or Resistive Random Access Memory (ReRAM) is a novel Non-Volatile Memory (NVM) with storage and computing functions, and it is the basic device of non-Von Neumann computer architecture which is Processing In Memory (PIM). To solve the speed mismatch problem between computing speed and storage of reconfigurable array processor, the model of Voltage ThrEshold Adaptive Memristor (VTEAM) is adopted. And through the simulation of Linear Technology Simulation Program with Integrated Circuit Emphasis (LTSPICE), the complete set of Boolean logic is realized. On this basis, a 1T1M memristor cross array is designed, which has the characteristics of simple structure, reconfiguration and high parallelism. Monte Carlo (MC) method is used for tolerance analysis, and the calculation accuracy had reached 0.998. Compared with the existing advanced array, the performance of this array is improved effectively, the processing delay and energy consumption are reduced, and this array can be combined with the reconfigurable array processor to deal with the “memory wall” problem.
- Processing In Memory (PIM) /
- Memristor /
- Array /
- Reconfigurable

HTML全文

图 1 VTEAM在LTSPICE中的模型子电路

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图 2 VTEAM模型在正弦波激励下的I-V特性

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图 3 MRL与逻辑运算单元

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图 4 MRL或逻辑运算单元

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图 5 MRL非逻辑运算单元

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图 6 MRL逻辑运算仿真曲线

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图 7 电压源MC参数

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图 8 电阻MC参数

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图 9 基于忆阻器的PIM基本电路结构

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图 10 阵列电路

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图 11 4×4阵列

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图 12 外围电路

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图 13 阵列仿真波形

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表 1 忆阻器VTEAM模型参数

参数	β	V_th	R_init	R_on	R_off
数值	e13	±0.8 V	10 kΩ	160 Ω	11 kΩ

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表 2 NMOS具体参数

参数	V_ds	R_ds	Q_gate
数值	12 V	0.003 Ω	3.6e-8 C

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表 3 逻辑运算单元比较

设计	逻辑单元	变量	读/写电路	延迟(Cycles)
IMP^[19]	AND	电阻值	需要	2
	OR	电阻值	需要	3
	NOT	电阻值	需要	1
MAGIC^[21]	AND	电阻值	需要	4
	OR	电阻值	需要	2
	NOT	电阻值	需要	1
FELIX^[23]	AND	电阻值	需要	2
	OR	电阻值	需要	1
	NOT	电阻值	需要	1
MRL	AND	电压值	不需要	1
	OR	电压值	不需要	1
	NOT	电压值	不需要	1

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表 4 1×4阵列、4×1阵列电路性能

阵列	输入值	输出值	功能
1×4	4	1	叠加
4×1	4	1	AND

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表 5 不同阵列比较情况

模型	存储单元	读/写电路	延时(ns/bit)	功耗(fW/bit)	是否重构	并行读取
文献[10]	1T2M	需要	3.00	24410.0	否	支持
文献[11]	1T2M	需要	0.01	150.0	否	支持
文献[12]	1TxM	需要	1.54	396.8	否	不支持
本文	1T1M	不需要	0.01	135.7	是	支持

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参考文献(24)

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