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面向心电检测的混合多模卷积神经网络加速器设计

刘冬生 魏来 邹雪城 陆家昊 成轩 胡昂 李德建 赵旭 蒋曲明

刘冬生, 魏来, 邹雪城, 陆家昊, 成轩, 胡昂, 李德建, 赵旭, 蒋曲明. 面向心电检测的混合多模卷积神经网络加速器设计[J]. 电子与信息学报, 2023, 45(1): 33-41. doi: 10.11999/JEIT220534
引用本文: 刘冬生, 魏来, 邹雪城, 陆家昊, 成轩, 胡昂, 李德建, 赵旭, 蒋曲明. 面向心电检测的混合多模卷积神经网络加速器设计[J]. 电子与信息学报, 2023, 45(1): 33-41. doi: 10.11999/JEIT220534
LIU Dongsheng, WEI Lai, ZOU Xuecheng, LU Jiahao, CHENG Xuan, HU Ang, LI Dejian, ZHAO Xu, JIANG Quming. Design of Hybrid Multimode Convolutional Neural Network Accelerator for Electrocardiogram Detection[J]. Journal of Electronics & Information Technology, 2023, 45(1): 33-41. doi: 10.11999/JEIT220534
Citation: LIU Dongsheng, WEI Lai, ZOU Xuecheng, LU Jiahao, CHENG Xuan, HU Ang, LI Dejian, ZHAO Xu, JIANG Quming. Design of Hybrid Multimode Convolutional Neural Network Accelerator for Electrocardiogram Detection[J]. Journal of Electronics & Information Technology, 2023, 45(1): 33-41. doi: 10.11999/JEIT220534

面向心电检测的混合多模卷积神经网络加速器设计

doi: 10.11999/JEIT220534
基金项目: 国家自然科学基金(62134002),国家重点研发计划(2021YFA0715502),湖北省重点研发项目(YFYB2020000413),东莞引进创新科研团队计划(201760712600139)
详细信息
    作者简介:

    刘冬生:男,博士,教授,研究方向为能效无线传输技术及芯片设计、后量子密码算法及密码芯片设计

    魏来:男,硕士生,研究方向为CNN硬件加速

    邹雪城:男,博士,教授,研究方向为超大规模集成电路

    陆家昊:男,博士生,研究方向为AI架构与处理器

    成轩:男,硕士生,研究方向为AI算法高效硬件实现

    胡昂:男,博士,研究方向为射频SoC

    李德建:女,硕士,研究方向为载波通信、低功耗设计

    赵旭:男,博士,研究方向为载波通信、无线通信

    蒋曲明:女,硕士,研究方向为电磁场与微波技术

    通讯作者:

    魏来 wei1123212130@163.com

  • 中图分类号: TN402

Design of Hybrid Multimode Convolutional Neural Network Accelerator for Electrocardiogram Detection

Funds: The National Natural Science Foundation of China (62134002), The National Key Research and Development Program of China (2021YFA0715502), The Key Research and Development Project of Hubei Province (YFYB2020000413), The Introduced Innovative R&D Team Program of Dongguan (201760712600139)
  • 摘要: 随着医疗资源日益匮乏以及人口老龄化日趋严重,心血管疾病已对人类健康造成了极大的威胁。具有心电(ECG)检测的便携式设备能有效降低心血管疾病对患者的威胁,因此该文设计了一种面向心电检测的混合多模卷积神经网络加速器。该文首先介绍了一种用于心电信号分类的1维卷积神经网络(1D-CNN)模型,随后针对该模型设计了一种高效的卷积神经网络(CNN)加速器,该加速器采用了一种多并行展开策略和多数据流的运算模式完成了卷积循环的加速和优化,能在时间上和空间上高度复用数据,同时提高了硬件资源利用率,从而提升了硬件加速器的硬件效率。最后基于Xilinx ZC706硬件平台完成了原型验证,结果显示,所设计卷积神经网络加速器消耗的资源为2247 LUTs, 80 DSPs。在200 MHz的工作频率下,该设计的整体性能可达到28.1 GOPS,并且硬件效率达到了12.82 GOPS/kLUT。
  • 图  1  各类型ECG信号的波形特征

    图  2  卷积层运算的4级循环

    图  3  全连接层运算的两级循环

    图  4  1D-CNN模型结构图[13]

    图  5  各层计算对应的运算模式

    图  6  3D-PE阵列结构

    图  7  CNN加速器的总体硬件架构

    图  8  FPGA硬件分类结果的混淆矩阵

    表  1  软硬件平台测试集的性能指标(%)

    平台AccSenSpecPpr
    Intel Core i5-1040099.2097.9799.6098.80
    ZYNQ 7000 ZC70699.1997.9299.6098.80
    下载: 导出CSV

    表  2  CNN加速器性能比较

    文献FPGABit-widthCNN ModelClock
    (MHz)
    DSP
    Utilization
    Resource
    (kLUT)
    Throughput
    (GOPS)
    Efficiency
    (GOPS/kLUT)
    DSP Efficiency
    (GOPS/DSP)
    [7]Arria 10
    GX 1150
    16 bit FixedVGG-162003036235k1030.24.3840.339
    [17]Zynq XC7Z04516 bit FixedVGG-16150780183k137.00.7490.175
    [18]Zynq
    ZCU 102
    16 bit FixedVGG-162001352390k495.41.2700.366
    [19]Zynq XC7Z04516 bit FixedVGG-1617257659k316.25.3580.549
    本设计Zynq ZC70616 bit Fixed1D-CNN200802.2k28.112.8200.360
    下载: 导出CSV
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出版历程
  • 收稿日期:  2022-04-28
  • 修回日期:  2022-06-18
  • 网络出版日期:  2022-06-28
  • 刊出日期:  2023-01-17

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