存内计算芯片研究进展及应用

郭昕婕; 王光燿; 王绍迪

doi:10.11999/JEIT220420

存内计算芯片研究进展及应用

doi: 10.11999/JEIT220420

1.
北京知存科技有限公司北京 100191
2.
北京航空航天大学集成电路科学与工程学院北京 100191

基金项目: 科技部“科技助力经济2020”重点专项项目(SQ2020YFF0404823)

详细信息

作者简介:
郭昕婕：女，博士，研究方向为存算一体芯片设计

王光燿：男，硕士生，研究方向为存算一体芯片设计

王绍迪：男，博士，研究方向为存储器及存算一体架构设计

通讯作者:
王绍迪　shaodi.wang@witintech.com

中图分类号: TN4
计量
- 文章访问数: 1524
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- PDF下载量: 465
- 被引次数: 0
出版历程
- 收稿日期: 2022-04-08
- 修回日期: 2022-10-09
- 网络出版日期: 2022-10-20
- 刊出日期: 2023-05-10

Technology Developments and Applications of In-memory Computing Processors

1.
Beijiing Zhicun (Witmem) Technology Corporation Limited, Beijing 100191, China
2.
School of Integrated Circuit Science and Engineering, Beihang University, Beijing 100191, China

Funds: The Ministry of Science and Technology's Key Special Project (SQ2020YFF0404823)

摘要

摘要: 随着数据快速增长，冯诺依曼架构内存墙成为计算性能进一步提升的关键瓶颈。新型存算一体架构(包括存内计算(IMC)架构与近存计算(NMC)架构)，有望打破冯诺依曼架构瓶颈，大幅提高算力和能效。该文介绍了存算一体芯片的发展历程、研究现状以及基于各类存储器介质(如传统存储器DRAM, SRAM和Flash和新型非易失性存储器ReRAM, PCM, MRAM, FeFET等)的存内计算基本原理、优势与面临的问题。然后，以知存科技WTM2101量产芯片为例，重点介绍了存算一体芯片的电路结构与应用现状。最后，分析了存算一体芯片未来的发展前景与面临的挑战。
- 存算一体 /
- 存储墙 /
- 功耗墙 /
- 存内计算 /
- 近存计算 /
- 冯诺依曼架构瓶颈
Abstract: Memory wall has become one of the key challenges in Von Neumann architecture, memory-centric computing architectures, such as In-Memory Computing (IMC) and Near-Memory Computing (NMC) are expected to break the Von-Neumann bottleneck, improving computing performance and energy efficiency. The progress of memory-centric computing technology, as well as the principles, advantages and problems based on a variety of memory media, such as traditional memories (e.g., DRAM, SRAM and Flash) and emerging non-volatile memories (e.g., ReRAM, PCM, MRAM and FeFET) are introduced in this paper. Then, the circuit structure and main applications with IMC chips are highlighted, taking Witmem's product WTM2101 as an example. Finally, the future development prospects and challenges of the all-in-one chip are also analysed.
- Memory-centric computing /
- Memory wall /
- Power wall /
- In-Memory Computing (IMC) /
- Near-Memory Computing (NMC) /
- Von-Neumann bottleneck

HTML全文

图 1 计算架构的演变示意图

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图 2 基于不同存储介质的计算架构演变图^[39]

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图 3 基于SRAM的存内计算单元结构

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图 4 基于DRAM的存内计算基本原理^[43]

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图 5 基于ReRAM的存内计算阵列结构与测试芯片

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图 6 基于MRAM的存内计算阵列布局图、显微图和结构^[49]

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图 7 基于NOR Flash的存内计算技术原理与相关产品

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图 8 WTM2101的阵列结构与芯片架构

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图 9 WTM2101存内计算芯片8 bit精度运算测试结果

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图 10 搭载WTM2101的耳机产品与WTM2101自动化部署流程

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图 11 WTM2101降噪性能图

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表 1 基于不同存储介质的存内计算芯片性能比较

标准	SRAM	DRAM	Flash	ReRAM	PCM	FeFET	MRAM
非易失性	否	否	是	是	是	是	是
多比特存储能力	否	否	是	是	是	是	否
面积效率	低	一般	高	高	高	高	高
功耗效率	低	低	高	高	高	高	高
工艺微缩性	好	好	较差	好	较好	好	好
成本	高	较高	低	低	较低	低	低
技术成熟度	测试芯片	测试芯片	量产产品	测试芯片	测试芯片	器件	测试芯片

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表 2 神经网络的累计余弦相似度

神经网络	累计余弦相似度
第0层	0.993
第1层	0.996
第2层	0.997
第3层	0.998
第4层	0.998
第5层	0.997
第6层	0.994
整个神经网络	0.994

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表 3 WTM2101与市场同类产品的性能比较

标准	市场现有同类产品		WTM2101
标准	算力复杂度(Mops)	功耗(mA)	算力复杂度(Mops)	功耗(mA)
语音激活检测	0.1	0.1	0.1	0.07
语音唤醒	20	0.6	400	0.4
40命令词识别	30	2	400	0.6
100命令词识别	100	10	400	0.8
环境去噪	150	15	800	1
声纹识别	1500	150	1500	2

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