基于静态随机存取存储器的存内计算研究进展

蔺智挺; 徐田; 童忠瑱; 吴秀龙; 汪方铭; 彭春雨; 卢文娟; 赵强; 陈军宁

doi:10.11999/JEIT210896

基于静态随机存取存储器的存内计算研究进展

doi: 10.11999/JEIT210896

安徽大学电子信息工程学院合肥 230601

基金项目: 国家重点研发计划(2018YFB2202602)，国家自然科学基金 (61934005, 62074001, U19A2074)

详细信息

作者简介:
蔺智挺：男，教授，研究方向为集成电路设计、存内计算

徐田：女，硕士生，研究方向为集成电路设计

童忠瑱：男，硕士生，研究方向为集成电路设计

吴秀龙：男，教授，研究方向为集成电路设计

汪方铭：男，硕士生，研究方向为集成电路设计

彭春雨：男，副教授，研究方向为高速低功耗静态随机存储器及其可靠性设计

卢文娟：女，讲师，研究方向为低功耗高能效集成电路设计

赵强：男，讲师，研究方向为SRAM存储单元的抗辐射

陈军宁：男，教授，研究方向为超大规模集成电路设计

通讯作者:
吴秀龙　xiulong@ahu.edu.cn

中图分类号: TN47
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- 被引次数: 0
出版历程
- 收稿日期: 2021-08-30
- 修回日期: 2021-10-28
- 网络出版日期: 2021-11-19
- 刊出日期: 2022-11-14

Research on Progress of Computing In-Memory Based on Static Random-Access Memory

Electronic and Information Engineering, Anhui University, Hefei 230601, China

Funds: The National Key Research and Development Program of China (2018YFB2202602), The National Natural Science Foundation of China (61934005, 62074001, U19A2074)

摘要

摘要: 随着“算力时代”到来，大规模数据需要在存储器和处理器之间往返，然而传统冯·诺依曼架构中计算与存储分离，无法满足频繁访问的需求。存内计算(CIM)技术的诞生突破了冯·诺依曼瓶颈，打破了传统计算架构中的“存储墙”，因此对于“算力时代”具有革命性意义。由于静态随机存取存储器(SRAM)读取数据的速度快且与先进逻辑工艺具有较好的兼容性，因此基于SRAM的存内计算技术受到国内外学者的关注。该文主要概述了基于SRAM的存内计算技术在机器学习、编码、加解密算法等方面的应用；回顾了实现运算功能的各种电路结构，比较了各类以模数转换器(ADC)为核心的量化技术；之后分析了现有存内计算架构面临的挑战并且给出了现有的解决策略，最后从不同方面展望存内计算技术。
- 静态随机存取存储器 /
- 存内计算 /
- 人工智能 /
- 卷积神经网络 /
- 模数转换器
Abstract: With the arrival of the “computing power era”, large-scale data need to go back and forth between the memory and the processor. However, the demand for frequent access can not be achieved in the traditional Von Neumann architecture which separates the computing and storage. The Von Neumann bottleneck and the “storage wall” in the traditional computing architecture have been broken with the birth of Computing In-Memory (CIM) Static Random-Access Memory technique. Thereby, for the “computing power era” it has revolutionary significance. Due to Static Random-Access Memory (SRAM) reads data fast and has better compatibility with advanced logic technology. Therefore, the attention of scholars at domestic and international has been attracted by SRAM-based CIM technology. The application of SRAM-based CIM technology is summarized, including machine learning, coding, encryption and decryption algorithm. The various circuit structures to realize the operation function and various quantization techniques based on Analog-to-Digital Conversion (ADC) are summarized and compared in this paper. In addition, the problems and challenges of the existing CIM architectures are analyzed. Then some existing solution strategies for those issues also are presented. Finally, the technique of SRAM-based CIM is prospected from different aspects.
- Static Random-Access Memory (SRAM) /
- Computing In-Memory (CIM) /
- Artificial Intelligence (AI) /
- Convolutional Neural Networks (CNN) /
- Analogue-to-Digital Converter (ADC)

HTML全文

图 1 SRAM阵列应用于卷积神经网络

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图 2 AES流程图

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图 3 布尔运算

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图 4 乘法运算

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图 5 减法运算原理图

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图 6 二进制内容可寻址

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图 7 三进制内容可寻址

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图 8 数字辅助型ADC

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图 9 晶体管尺寸加权

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图 10 电容加权技术

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图 11 脉冲加权

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图 12 共源共栅电流镜

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图 13 多行读取的读破坏

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图 14 电路单元库模型实例

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图 15 计算资源调度方式研究方案

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图 16 面向CIM的异构多处理器系统关键技术的研究思路

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表 1 CIM实现布尔运算的相关设计参数以及性能指标

	文献[2]	文献[26]	文献[29]	文献[31]	文献[33]
传输管工艺阵列大小	8T/8T+	8T	8T	6T	8T
	45 nm PTM	180 nm	22 nm FD-SOI	28 nm	65 nm
	NA	NA	4 kB	16 kb	16 kb
功耗每bit(fJ)	8T:17.25 8T⁺:29.67	21.84	248 (0.9 V)	23.8	16.6 (0.8 V) 13.2 (0.6 V)
功能	NAND/XOR/ NOR/RCS	NAND/AND/NOR/ OR/XOR	AND/OR (multi_row selsction)	NOR/AND/XOR	AND/NAND /NOR/OR/ XOR/XNOR
特点	8T:读写分离 8T⁺:读写分离，非对称SA检测	读写分离	读写分离	局部位线	4输入的布尔逻辑运算

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表 2 存内实现乘法运算的参数以及性能指标

	文献[3]		文献[4]	文献[12]	文献[11,13]	文献[14]	文献[37]	文献[18,19]	文献[40]
单元类型	6T		8T1C	10T	8T	10T	Twin-8T	6T	6T
工艺(nm)	65		65	65	7	45	55	130	55
阵列大小(Kb)	64		2	16	4	8	3.75	16	4
输入(bit)	5		1	6	4	1	1, 2, 4	5	1, 2, 7, 8
权重(bit)	5		1	1	4	1	2, 5	1	1, 2, 8
能效TOPS/W	NA		671.5	40.3(1 V)	351(0.8 V)	NA	singles channel:18.4-72.0	NA	0.6～40.2(0.9 V)
面积(μm²)	NA		8.1×10⁴	6.3×10⁴	3.2×10³	NA	4.69×10⁴	2.67×10⁵	5.94×10⁶
精确度(%)	MINST	99.05	98.31	>98	>99	NA	90.02～99.52	>90	>98
精确度(%)	CIFAR10	88.83	83.50	NA	>88	约89	85.56～90.42	NA	>85

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表 3 存内CAM芯片参数以及性能指标总结

	文献[9]		文献[10]		文献[33]		文献[41]	文献[42]
阵列大小	BCAM:4 kb		16 kb		16 kb		8 kb	16 kb
阵列大小	TCAM:2 kb		16 kb		16 kb		8 kb	16 kb
单元类型	6T		4+2T		8T		6T	9T
工艺(nm)	28		55		65		28	65
功能	BCAM/TCAM/ SRAM/Logic		BCAM/TCAM/Logic		BCAM/TCAM/ SRAM/Logic		BCAM/SRA/ Pseudo-TCAM	BCAM
功耗每bit(fJ)	BCAM:0.6	(1 V)	BCAM:0.45	(0.8 V)	BCAM:0.24	(0.6 V)	0.13(0.9 V)	BCAM:2.07	(0.4 V)
功耗每bit(fJ)	TCAM:0.74	(1 V)	BCAM:0.45	(0.8 V)	TCAM:0.41	(0.6 V)	0.13(0.9 V)	BCAM:2.07	(0.4 V)

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