一种高性能硬件加密引擎阵列架构

骆建军; 沈一凡; 周迪; 冯春阳; 邓江峡

doi:10.11999/JEIT200855

一种高性能硬件加密引擎阵列架构

doi: 10.11999/JEIT200855

1.
杭州电子科技大学微电子研究中心杭州 310018
2.
浙江宇视科技有限公司杭州 310051

基金项目: 国家基础科研项目(JCKY2018415C001)，浙江省固态硬盘和数据安全技术重点实验室(2015E10003)

详细信息

作者简介:
骆建军：男，1970年生，教授，博士生导师，研究方向为集成电路、数字存储和数据安全系统

沈一凡：女，1996年生，硕士，研究方向为集成电路

周迪：男，1975年生，正高级工程师，研究方向为物联网、视频安全

冯春阳：男，1966年生，高级工程师，研究方向为集成电路设计、功率半导体

邓江峡：女，1983年生，副教授、硕士生导师，研究方向为自旋电子学、集成电路设计与验证

通讯作者:
邓江峡　dengjiangxia@hdu.edu.cn

中图分类号: TN492; TN918.4
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- 被引次数: 0
出版历程
- 收稿日期: 2020-10-04
- 修回日期: 2021-09-30
- 网络出版日期: 2021-10-25
- 刊出日期: 2021-12-21

High Performance Crypto Module with Array of Hardware Engines

1.
Microelectronics Research Institute of Hangzhou Dianzi University, Hangzhou 310018, China
2.
Uniview Research Institute, Hangzhou 310051, China

Funds: The National Basic Research Program (JCKY2018415C001), Zhejiang Key Laboratory Foundation of Solid State Drive and Data Security (2015E10003)

摘要

摘要: 该文提出一种高性能硬件加密引擎阵列架构，为大数据应用提供了先进的安全解决方案。该模块架构包括一个高速接口、一个中央管理和监视模块(CMMM)、一组多通道驱动加密引擎阵列，其中CMMM将任务分配给加密引擎，经由专用算法处理后再将数据传回主机。由于接口吞吐量和加密引擎阵列规模会限制模块性能，针对PCIe高速接口，采用MMC/eMMC总线连接构建阵列，发现更多加密引擎集成到系统后，模块性能将会得到提升。为验证该架构，使用55 nm制程工艺完成了一个PCIe Gen2×4接口的ASIC加密卡，测试结果显示其平均吞吐量高达419.23 MB。
- 专用集成电路 /
- 安全 /
- 加密 /
- PCIe /
- eMMC
Abstract: A high-performance crypto module prescribed in this paper offers advanced security solutions in big data applications. A module architecture, which consists of a high throughput interface, Central Manage & Monitor Module (CMMM) and multiple channels driving a group of crypto engines, is discussed here. CMMM distributes the tasks to the crypto engines and guides the data back to the host after processing by the dedicated algorithm. Since the module's performance is limited by the interface throughput and the scale of the crypto engines, an array with MMC/eMMC bus connections is built for PCIe high-speed interfaces. The more crypto engines are integrated into a system, the higher performance of this system can reach. To verify this architecture, an ASIC encryption card with PCIe Gen2×4 interface is made under semiconductor manufacturing process technology of 55 nm, and tested. The average throughput of this card can achieve up to 419.23 MB.
- ASIC /
- Security /
- Crypto /
- PCIe /
- eMMC

HTML全文

图 1 加密模块架构

下载: 全尺寸图片幻灯片

图 2 使用MMC接口的加密块

下载: 全尺寸图片幻灯片

图 3 加密引擎结构

下载: 全尺寸图片幻灯片

图 4 加密任务流程

下载: 全尺寸图片幻灯片

图 5 一个MMC主机驱动多个MMC设备

下载: 全尺寸图片幻灯片

图 6 MMC设备在CMD信号上“线与”

下载: 全尺寸图片幻灯片

表 1 不同情况下的最大总时延(ms)

	N=1	N=2	N=4	N=8
M=1	24007	12008	6010	3014
M=8	3014	1522	788	445

下载: 导出CSV

表 2 性能测试

	#1	#2	#3	#4
连续读(MB/s)	1105.00	1102.00	1103.00	1103.00
连续写(MB/s)	912.60	912.10	912.00	912.20
随机读(k-IOPS)	50.85	84.98	82.83	85.23
随机写(k-IOPS)	105.00	104.75	104.75	104.73
吞吐率(MB/s)	420.00	419.00	419.00	428.92

下载: 导出CSV

表 3 随机读写的时延(μs)

	平均时延	最大时延
随机读(4 kB)	53	1894
随机写(4 kB)	24	1039

下载: 导出CSV

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