Rollback Cyclic Redundancy Check Algorithm in High Bit-width
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摘要: 为解决大位宽变长数据包情况下包尾数据的循环冗余校验(CRC)32算法处理存在的臃肿低效问题，将循环冗余校验算法变换为矩阵线性运算，利用逆矩阵反向回滚运算，得到正确的CRC运算结果；并在FPGA上进行了实验验证。结果表明：回滚运算的算法可行，并且实现简单，资源占用少。在512 bit位宽的情况下，回滚算法使得资源占用降低到了传统算法的15%；综合耗时降低到了传统算法的30%，布局/布线的耗时降低到了传统算法的40%。Abstract: In order to overcome the complicated implementation to process tail data in high bit-width Cyclic Redundancy Check(CRC) calculation for variable length packet, linear matrix computation is used to investigate CRC inverse calculation. And a rollback algorithm is introduced to simplify the regular algorithm. Then the experiment is conducted to implement the rollback algorithm in Altera FPGA device. The results show that rollback algorithm utilizes fewer resource and is more easily to implement. In 512 bit data width variable length CRC calculation implement in FPGA, the resource utilization is decreased to 15% of regular algorithm by applying rollback algorithm. Synthesis time is decreased to 30%, and Place&Route time is deceased to 40%. It is concluded that the new rollback algorithm has great advantage.
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Key words:
- Cyclic Redundancy Check(CRC) /
- FPGA /
- Matrix linear computation /
- Rollback
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表 1 实验环境
项目 规格 备注 器件厂家/型号 Altera/ 5CEFA7U19C7 Cyclone–V系列 开发软件 Quartus II 13.1 (64–bit) V13.1 开发平台 便携PC机 – 操作系统 Win10 – CPU Core–8250U 4核 主频 1.6 GHz – 内存 8 GB DDR4 
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