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一种快速响应无片外电容低压差线性稳压器

佟星元 李茂 董嗣万

佟星元, 李茂, 董嗣万. 一种快速响应无片外电容低压差线性稳压器[J]. 电子与信息学报, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060
引用本文: 佟星元, 李茂, 董嗣万. 一种快速响应无片外电容低压差线性稳压器[J]. 电子与信息学报, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060
Xingyuan TONG, Mao LI, Siwan DONG. A Capacitor-less Low Dropout Regulator with Fast Response[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060
Citation: Xingyuan TONG, Mao LI, Siwan DONG. A Capacitor-less Low Dropout Regulator with Fast Response[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060

一种快速响应无片外电容低压差线性稳压器

doi: 10.11999/JEIT181060
基金项目: 国家自然科学基金(61674122,61804124),陕西省创新人才推进计划(2017KJXX-46),陕西省高层次人才特殊支持计划(2018-36)
详细信息
    作者简介:

    佟星元:男,1984年生,博士后,教授,研究方向为生物医疗电子、超低功耗模拟. 混合信号集成电路设计

    李茂:男,1994年生,硕士生,研究方向为电源管理及无线能量传输电路设计

    董嗣万:男,1988年生,博士,讲师,研究方向为模拟集成电路设计

    通讯作者:

    佟星元 mayxt@126.com

  • 中图分类号: TN431.2

A Capacitor-less Low Dropout Regulator with Fast Response

Funds: The National Natural Science Foundation of China (61674122, 61804124), Shaanxi Innovation Talents Promotion Plan(2017KJXX-46), Shaanxi Provincial High-level Talents Special Support Plan (2018-36)
  • 摘要: 为了改善负载跳变对低压差线性稳压器(LDO)的影响,该文提出一种用于无片外电容LDO(CL-LDO)的新型快速响应技术。通过增加一条额外的快速通路,实现CL-LDO的快速瞬态响应,并且能够减小LDO输出过冲和下冲的幅度。该文电路基于0.18 μm CMOS工艺设计实现,面积为0.00529 mm2。流片测试结果表明,当输入电压范围为1.5~2.5 V时,输出电压为1.194 V;当负载电流以 1 μs的上升时间和下降时间在 100 μA~10 mA之间变化时,CL-LDO的过冲恢复时间为489.537 ns,下冲恢复为960.918 ns;相比未采用该技术的传统CL-LDO,响应速度能够提高7.41倍,输出过冲和下冲的电压幅值能够分别下降35.3%和78.1%。
  • 图  1  传统LDO和CL-LDO结构

    图  2  本文提出CL-LDO的整体结构

    图  3  本文提出CL-LDO的工作原理

    图  4  本文提出的快速瞬态调节电路

    图  5  本文CL-LDO的小信号模型等效电路

    图  6  环路特性仿真结果

    图  7  本文提出CL-LDO的芯片照片和版图

    图  8  本文CL-LDO的瞬态测试结果

    图  9  本文CL-LDO的直流特性测试结果

    表  1  控制信号Ctrl1和Ctrl2的工作原理

    ILVfbCtrl1Ctrl2M1M2
    升高下冲/<0.70 V低电平低电平导通关断
    降低过冲/>0.90 V高电平高电平关断导通
    稳定稳定/=0.80 V高电平低电平关断关断
    下载: 导出CSV

    表  2  本文设计的CL-LDO与其它文献的CL-LDO性能比较

    参数文献[13]*文献[14]文献[15]文献[16]本文
    W/OW
    工艺 (nm)18065180130180
    Vin (V)1.21.21.2~1.81~1.41.5~2.5
    Vout (V)110.8~1.60.81.2
    IL (mA)1000.1~251-1000.12~250.1~10
    过冲/下冲 (mV)220225200284597/946386/207
    环路增益 (dB)>59.87585~8785~87
    负载调整率 (mV/mA)0.0230.0420.0810.1730.970.96
    线性调整率 (mV/V)0.693.82.2511.310.0
    恢复时间 (μs)3.61.30.220.19#3.6240.489
    电源抑制比 (dB)49.6525750.2
    面积 (mm2)0.0220.0870.0310.0080.00529
    *考虑寄生参数的电路后仿真数据;电流阶跃变化的上升时间和下降时间为1 μs;电流阶跃变化的上升时间和下降时间约为300 ps;#电流阶跃变化的上升时间和下降时间约为100 ns。
    下载: 导出CSV
  • MILLIKEN R J, SILVA-MARTINEZ J, and SANCHEZ-SINENCIO E. Full on-chip CMOS low-dropout voltage regulator[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2007, 54(9): 1879–1890. doi: 10.1109/TCSI.2007.902615
    YEO J, JAVED K, LEE J, et al. A capacitorless low-dropout regulator with enhanced slew rate and 4.5-μA quiescent current[J]. Analog Integrated Circuits and Signal Processing, 2017, 90(1): 227–235. doi: 10.1007/s10470-016-0869-z
    TONG Xingyuan and SUN Tiantian. A programmable multi-output technique in LDO regulator for multi-reference SAR ADC application[J]. International Journal of Electronics, 2017, 104(3): 528–538. doi: 10.1080/00207217.2016.1218069
    HUANG W J, LU S H, and LIU Shenluan. A capacitor-free CMOS low dropout regulator with slew rate enhancement[C]. Proceedings of 2006 International Symposium on VLSI Design, Automation and Test, Hsinchu, China, 2006: 1–4.
    LIU Nanqi, JOHNSON B, NADIG V, et al. A transient-enhanced fully-integrated LDO regulator for SoC application[C]. Proceedings of 2018 IEEE International Symposium on Circuits and Systems, Florence, Italy, 2018: 1–5.
    LEUNG K N and NG Y S. A CMOS low-dropout regulator with a momentarily current-boosting voltage buffer[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2010, 57(9): 2312–2319. doi: 10.1109/TCSI.2010.2043171
    AL-SHYOUKH M, LEE H, and PEREZ R. A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation[J]. IEEE Journal of Solid-State Circuits, 2007, 42(8): 1732–1742. doi: 10.1109/JSSC.2007.900281
    TONG Xingyuan and WEI Kangkang. A fully integrated fast-response LDO voltage regulator with adaptive transient current distribution[C]. Proceedings of 2017 IEEE Computer Society Annual Symposium on VLSI, Bochum, Germany, 2017: 651–654.
    MARANO D, GRASSO A D, PALUMBO G, et al. Optimized active single-miller capacitor compensation with inner half-feedforward stage for very high-load three-stage OTAs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2016, 63(9): 1349–1359. doi: 10.1109/TCSI.2016.2573920
    ZENG Yanhan, LI Yuao, ZHANG Xin, et al. A push-pulled FVF based output-capacitorless LDO with adaptive power transistors[J]. Microelectronics Journal, 2017, 64: 69–77. doi: 10.1016/j.mejo.2017.04.008
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    AAMIR S A, HARIKUMAR P, and WIKNER J J. Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers[C]. Proceedings of 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, 2013: 381–384.
    SHIRMOHAMMADLI V, SABERKARI A, MARTINEZ-GARCIA H, et al. Low power output-capacitorless class-AB CMOS LDO regulator[C]. Proceedings of 2017 IEEE International Symposium on Circuits and Systems, Baltimore, USA, 2017: 1–4.
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出版历程
  • 收稿日期:  2018-11-20
  • 修回日期:  2019-03-07
  • 网络出版日期:  2019-04-10
  • 刊出日期:  2019-11-01

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