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FPGA硬核处理器系统加速数字电路功能验证的方法

刘小强 袁国顺 乔树山

刘小强, 袁国顺, 乔树山. FPGA硬核处理器系统加速数字电路功能验证的方法[J]. 电子与信息学报, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641
引用本文: 刘小强, 袁国顺, 乔树山. FPGA硬核处理器系统加速数字电路功能验证的方法[J]. 电子与信息学报, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641
Xiaoqiang LIU, Guoshun YUAN, Shushan QIAO. Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641
Citation: Xiaoqiang LIU, Guoshun YUAN, Shushan QIAO. Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641

FPGA硬核处理器系统加速数字电路功能验证的方法

doi: 10.11999/JEIT180641
基金项目: 国家自然科学基金(61474135)
详细信息
    作者简介:

    刘小强:男,1990年生,博士生,研究方向为SoC芯片设计、图像识别

    袁国顺:男,1966年生,博士生导师、研究员,研究方向为嵌入式MCU设计、高性能模数混合电路

    乔树山:男,1980年生,硕士生导师、研究员,研究方向为低功耗集成电路设计方法学、智能感知节点SoC、无线通信、电力线载波通信、数字化射频接收机、低功耗处理器

    通讯作者:

    袁国顺 mryuangs@hotmail.com

  • 中图分类号: TN492

Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System

Funds: The National Natural Science Foundation of China (61474135)
  • 摘要: 为了缩短专用集成电路和片上系统的功能验证周期,该文提出FPGA硬核处理器系统加速数字电路功能验证的方法。所提方法综合软件仿真功能验证和现场可编程门阵列原型验证的优点,利用集成在片上系统现场可编程门阵列器件中的硬核处理器系统作为验证激励发生单元和功能验证覆盖率分析单元,解决了验证速度和灵活性不能统一的问题。与软件仿真验证相比,所提方法可以有效缩短数字电路的功能验证时间;在功能验证效率和验证知识产权可重用方面表现优于现有的FPGA原型验证技术。
  • 图  1  软件仿真验证平台

    图  2  验证系统硬件实现图

    图  4  验证软硬件分割图

    图  3  功能验证技术的实现流程图

    图  5  不同验证技术对比结果

    表  1  本文提出的技术与其他文献的结果对比

    采用技术 功能覆盖率(%) 高级语言 验证时长(s) 通信带宽(Gb/s) 验证IP复用 频率(MHz)
    软件仿真验证[4,5] 100 203572
    传统FPGA原型验证[7,8] 594 63.5
    改进FPGA原型验证[9,10] 100 357 1.00 58.3
    本文所提出的技术 100 179 25.20 98.6
    下载: 导出CSV
  • WANG Yifan, JOERES S, WUNDERLICH R, et al. Modeling approaches for functional verification of RF-SoCs: Limits and future requirements[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009, 28(5): 769–773. doi: 10.1109/TCAD.2009.2014533
    MARKOVIC D, CHANG Chen, RICHARDS R, et al. ASIC design and verification in an FPGA environment[C]. Proceedings of 2007 IEEE Custom Integrated Circuits Conference, San Jose, USA, 2007: 737–740.
    STOTLAND I, SHPAGILEV D, and STARIKOVSKAYA N. UVM based approaches to functional verification of communication controllers of microprocessor systems[C]. Proceedings of 2016 IEEE East-West Design & Test Symposium, Yerevan, Armenia, 2016: 1–4.
    HU Zhaohui, PIERRES A, HU Shiqing, et al. Practical and efficient SOC verification flow by reusing IP testcase and testbench[C]. Proceedings of 2012 International SoC Design Conference, Jeju Island, South Korea, 2012: 175–178.
    KIM M, KONG J, SUH T, et al. Latch-based FPGA emulation method for design verification: Case study with microprocessor[J]. Electronics Letters, 2011, 47(9): 532–533. doi: 10.1049/el.2011.0462
    施佺, 韩赛飞, 黄新明, 等. 面向全同态加密的有限域FFT算法FPGA设计[J]. 电子与信息学报, 2018, 40(1): 57–62. doi: 10.11999/JEIT170312

    SHI Quan, HAN Saifei, HUANG Xinming, et al. Design of finite field FFT for fully homomorphic encryption based on FPGA[J]. Journal of Electronics &Information Technology, 2018, 40(1): 57–62. doi: 10.11999/JEIT170312
    LI Tiejun, ZHANG Jianmin, and LI Sikun. An FPGA-based random functional verification method for cache[C]. Proceedings of the 2013 IEEE 8th International Conference on Networking, Architecture and Storage, Xi'an, China, 2013: 277–281.
    GSCHWIND M, SALAPURA V, and MAURER D. FPGA prototyping of a RISC processor core for embedded applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001, 9(2): 241–250. doi: 10.1109/92.924027
    PODIVINSKY J, CEKAN O, LOJDA J, et al. Functional verification based platform for evaluating fault tolerance properties[J]. Microprocessors and Microsystems, 2017, 52: 145–159. doi: 10.1016/j.micpro.2017.06.004
    BARNASCONI M, DIETRICH M, EINWICH K, et al. UVM-systemC-AMS framework for system-level verification and validation of automotive use cases[J]. IEEE Design & Test, 2015, 32(6): 76–86. doi: 10.1109/MDAT.2015.2427260
    IEEE. 1800.2-2017 IEEE standard for universal verification methodology language reference manual[S]. IEEE, 2017.
    CHEN Fulong and SUN Yunxiang. FPGA-based elastic in-circuit debugging for complex digital logic design[J]. International Journal of Autonomous and Adaptive Communications Systems, 2017, 10(3): 303–319. doi: 10.1504/IJAACS.2017.10007621
    Intel FPGA. Cyclone V hard processor system technical reference manual[EB/OL]. https://www.altera.com/documentation/sfo1410143707420.html, 2018: 6.
    Xilinx Inc. Zynq-7000 all programmable SoC data sheet: Overview[EB/OL]. https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#documentation, 2018: 6.
    DUARTE-SÁNCHEZ J E, VELASCO-MEDINA J, and MORENO P A. Hardware accelerator for the multifractal analysis of DNA sequences[J]. IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2018, 15(5): 1611–1624. doi: 10.1109/TCBB.2017.2731339
    ISKANDER Y, PATTERSON C, and CRAVEN S. High-level abstractions and modular debugging for FPGA design validation[J]. ACM Transactions on Reconfigurable Technology and Systems, 2014, 7(1): 1–22. doi: 10.1145/2567662
    SCHAFER B C. Source code error detection in High-level synthesis functional verification[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(1): 301–312. doi: 10.1109/TVLSI.2015.2397036
  • 加载中
图(5) / 表(1)
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  • 被引次数: 0
出版历程
  • 收稿日期:  2018-07-02
  • 修回日期:  2018-01-10
  • 网络出版日期:  2019-01-22
  • 刊出日期:  2019-05-01

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