一种高效的混合Test-Per-Clock测试方法

刘铁桥; 牛小燕; 杨洁; 毛峰

doi:10.11999/JEIT161202

一种高效的混合Test-Per-Clock测试方法

doi: 10.11999/JEIT161202

基金项目:

浙江省自然科学基金(LQ15F040005)

计量
- 文章访问数: 1063
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- 被引次数: 0
出版历程
- 收稿日期: 2016-11-08
- 修回日期: 2017-04-10
- 刊出日期: 2017-09-19

An Efficient Mixed-mode Test-Per-Clock Scheme

Funds:

Zhejiang Provincial Natural Science Foundation (LQ15F040005)

摘要

摘要: 该文提出了一种基于内建自测试(BIST)的Test-Per-Clock混合模式向量产生方法。测试由两个部分组成：自由线性反馈移位寄存器(LFSR)伪随机测试模式和受控LFSR确定型测试模式。伪随机测试模式用于快速地检测伪随机易测故障，减少确定型数据存储。受控LFSR测试模式采用直接存储在ROM中的控制位流对剩余故障产生确定型测试。通过对提出的BIST混合模式测试结构理论分析，提出了伪随机向量的选取方法以及基于受控线性移位确定型测试生成方法。基准电路的仿真结果表明，该方法可以获得完全单固定型故障覆盖率，其测试产生器设计简单且具有良好的稳定性，与其他方法相比，具有较低的测试开销和较短的测试应用时间。
- IC测试 /
- 内建自测试 /
- Test-Per-Clock测试 /
- 测试生成
Abstract: A mixed-mode Test-Per-Clock Built In Self Test (BIST) scheme is proposed. The test consists of two parts: the free Linear Feedback Shift Register (LFSR) pseudo-random test mode and the deterministic test pattern based on controlled LFSR. Pseudo random test mode is used to quickly detect pseudo-random susceptible faults and reduce the deterministic data storage. Controlled LFSR test mode uses the control bits directly stored in the ROM to generate a deterministic test of the remaining faults. Based on the theoretical analysis of the proposed mixed-mode BIST test structure, a pseudo-random test sequence selection method and a deterministic test generation method based on controlled linear shifter are proposed. Simulation results on benchmark circuits show that the proposed method can obtain the complete single stuck-at fault coverage and has good stability in test generation. Compared with other methods, it has simpler Test Pattern Generator (TPG) design and lower test cost as well as shorter test application time.
- IC test /
- Built In Self Test (BIST) /
- Test-Per-Clock test /
- Test generation

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参考文献(21)

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