基于二极管单元的高密度掩模ROM设计

叶勇; 亢勇; 宋志棠; 陈邦明

doi:10.11999/JEIT160938

基于二极管单元的高密度掩模ROM设计

doi: 10.11999/JEIT160938

1.
(中国科学院上海微系统与信息技术研究所上海 200050) ②(上海新储集成电路有限公司上海 200122)

基金项目:

中国科学院战略性先导科技专项(XDA09020402)，国家重点基础研究发展计划(2013CBA01904, 2013CBA01900, 2010CB 934300, 2011CBA00607, 2011CB932804)，国家集成电路重大专项(2009ZX02023-003)，国家自然科学基金(61076121, 61176122, 61106001, 61261160500, 61376006)

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出版历程
- 收稿日期: 2016-09-19
- 修回日期: 2017-01-22
- 刊出日期: 2017-06-19

Design of High-density Mask ROM Based on Diode Cells

1.
(Shanghai Institute of Microsystem And Information Technology, Chinese Academy of Sciences, Shanghai 200050, China)
2.
(Shanghai Xinchu Integrated Circuit Incorporation, Shanghai 200122, China)

Funds:

Strategic Priority Research Program of the Chinese Academy of Sciences (XDA09020402), The National Key Basic Research Program of China (2013CBA01904, 2013CBA01900, 2010CB934300, 2011CBA00607, 2011CB932804), The National Integrate Circuit Research Program of China (2009ZX02023-003), The National Natural Science Foundation of China (61076121, 61176122, 61106001, 61261160500, 61376006)

摘要

摘要: 针对传统ROM(Read-Only Memory)存储密度低、功耗高的问题，该文提出一种采用二极管单元并通过接触孔编程来存储数据的掩模ROM。二极管阵列采用双沟槽隔离工艺和无间隙接触孔连接方式实现了极高的存储密度。基于此设计了一款容量为2 Mb的掩模ROM，包含8个256 kb的子阵列。二极管阵列采用40 nm设计规则，外围逻辑电路采用2.5 V CMOS工艺完成设计。二极管单元的有效面积仅为0.017m2，存储密度高达0.0268 mm2/Mb。测试结果显示二极管单元具备良好的单元特性，在2.5 V电压下2 Mb ROM的比特良率达到了99.8%。
- 掩模只读存储器 /
- 二极管阵列 /
- 高密度 /
- 低功耗 /
- 双沟槽隔离
Abstract: Since the traditional Read-Only Memory (ROM) has the problems of low density and high power consumption, a mask ROM based on diode cells and contact-programming process is proposed. With dual-trench isolation process and borderless contact scheme, the diode array can realize ultrahigh density. Based on the proposed novel diode array, a mask ROM macro with 2 Mb capacity is designed, which contains 8 256 kb sub-arrays. The diode arrays are fabricated with 40 nm design rule and the peripheral logic circuits are achieved in 2.5 V CMOS process. The effective area of the diode cell is only 0.017 m2 and the density of the diode array is 0.0268 mm2/Mb. Test results show that the cell feature of diodes is good and the bit yield of the 2 Mb ROM achieves 99.8% under 2.5 V supply voltage.
- Mask Read-Only Memory (ROM) /
- Diode array /
- High-density /
- Low power /
- Dual-trench isolation process

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参考文献(17)

LU S K, TSAI C J, and HASHIZUME M. Enhanced built-in self-repair techniques for improving fabrication yield and reliability of embedded memories[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(8): 2726-2734. doi: 10.1109/TVLSI.2016.2523499.

MOHAMMAD B S, SALEH H, and ISMAI M. Design methodologies for yield enhancement and power efficiency in SRAM-based SoCs[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(10): 2054-2064. doi: 10.1109/TVLSI.2014.2360319.

CHEN Y J, HUANG C E, CHEN H M, et al. A novel 2-bit/cell p-channel logic programmable cell with pure 90-nm CMOS technology[J]. IEEE Electron Device Letters, 2008, 29(8): 938-940. doi: 10.1109/LED.2008.2000969.

顾明, 杨军. 基于物理指数MOSFET模型的SRAM存储体单元优化[J]. 电子与信息学报, 2007, 29(1): 223-226.

GU M and YANG J. Optimization of SRAM memory cell based on physical alpha-power law MOSEFT model[J]. Journal of Electronics Information Technology, 2007, 29(1): 223-226.

KHANDELWAL S, RAJ B, and GUPTA R D. FinFET based 6T SRAM cell design: analysis of performance metric, process variation and temperature effect[J]. Journal of Computational and Theoretical Nanoscience, 2015, 12(9): 2500-2506. doi: 10.1166/jctn.2015.4055.

WANG J, WANG L, YIN H, et al. cNV SRAM: CMOS technology compatible non-volatile SRAM based ultra-low leakage energy hybrid memory system[J]. IEEE Transactions on Computers, 2016, 65(4): 1055-1067. doi: 10.1109/TC. 2014.2375187.

NARUSE M, KAMEI T, KUNIO T, et al. A 65 nm single- chip application and dual-mode baseband processor with partial clock activation and IP-MMU[J]. IEEE Journal of Solid-State Circuits, 2009, 44(1): 83-89. doi: 10.1109/JSSC. 2008.2007169.

KULKARNI S H, CHEN Z, HE J, et al. A 4 kb metal-fuse OTP-ROM macro featuring a 2V programmable 1.37 m2 1T1R bit cell in 32 nm high-k metal-gate CMOS[J]. IEEE Journal of Solid-State Circuits, 2010, 45(4): 863-868. doi: 10.1109/JSSC.2010.2040115.

LIU Z, ZHENG R, and SUN J. A gate-oxide-breakdown antifuse OTP ROM array based on TSMC 90 nm process[C]. 2015 International Symposium on Next-Generation Electronics (ISNE), Taipei, China, 2015: 1-3. doi: 10.1109/ ISNE.2015.7132015.

KULKARNI S H, CHEN Z, SRINIVASAN B, et al. A high- density metal-fuse technology featuring a 1.6 V programmable low-voltage bit cell with integrated 1 V charge pumps in 22 nm tri-gate CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(4): 1003-1008. doi: 10.1109/ JSSC.2015.2507786.

CHANG M F and YANG S M. Analysis and reduction of supply noise uctuations induced by embedded via- programming ROM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009, 17(6): 758-769. doi: 10.1109/TVLSI.2008.2006794.

JANG B J, LEE C H, SIM S H, et al. Robust via- programmable ROM design based on 45 nm process considering process variation and enhancement Vmin and yield[C]. IEEE International Symposium on Circuits and Systems (ISCAS), Piscataway, USA, 2015: 2541-2544. doi: 10.1109/ISCAS.2015.7169203.

UMEMOTO Y, NII Y, ISHIKAWA J, et al. 28 nm 50% power-reducing contacted mask read only memory macro with 0.72 ns read access time using 2T pair bitcell and dynamic column source bias control technique[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(3): 575-584. doi: 10.1109/TVLSI.2013.2246201.

HUANG C E, CHEN Y J, LAI H C, et al. A study of self-　aligned nitride erasable OTP cell by 45-nm CMOS fully compatible process[J]. IEEE Transactions on Electron Device, 2009, 56(6): 1228-1234. doi: 10.1109/TED.2009.2018169.

YANG S M, CHANG M F, CHIANG C C, et al. Low-voltage embedded NAND-ROM macros using data-aware sensing reference scheme for VDDmin, speed and power improvement [J]. IEEE Journal of Solid-State Circuits, 2013, 48(2): 611-623. doi: 10.1109/JSSC.2012.2229068.

CHANG M F, YANG S M, LIANG C W, et al. Noise-immune embedded NAND ROM using a dynamic split source-line scheme for VDDmin and speed improvements[J]. IEEE Journal of Solid-State Circuits, 2010, 45(10): 2142-2155. doi: 10.1109/JSSC.2010.2060279.

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