40 nm CMOS工艺下的低功耗容软错误锁存器

黄正峰; 王世超; 欧阳一鸣; 易茂祥; 梁华国

doi:10.11999/JEIT160889

40 nm CMOS工艺下的低功耗容软错误锁存器

doi: 10.11999/JEIT160889

1.
(合肥工业大学电子科学与应用物理学院合肥 230009) ②(合肥工业大学计算机与信息学院合肥 230009)

基金项目:

国家自然科学基金(61574052, 61371025, 61474036, 61674048)，安徽省自然科学基金(1608085MF149)

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- 被引次数: 0
出版历程
- 收稿日期: 2016-09-02
- 修回日期: 2017-02-22
- 刊出日期: 2017-06-19

Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology

1.
(School of Electronic Science &
2.
(School of Computer &

Funds:

The National Natural Science Foundation of China (61574052, 61371025, 61474036, 61674048), The Natural Science Foundation of Anhui Province (1608085MF149)

摘要

摘要: 为了降低集成电路的软错误率，该文基于时间冗余的方法提出一种低功耗容忍软错误锁存器。该锁存器不但可以过滤上游组合逻辑传播过来的SET脉冲，而且对SEU完全免疫。其输出节点不会因为高能粒子轰击而进入高阻态，所以该锁存器能够适用于门控时钟电路。SPICE仿真结果表明，与同类的加固锁存器相比，该文结构仅仅增加13.4%的平均延时，使得可以过滤的SET脉冲宽度平均增加了44.3%，并且功耗平均降低了48.5%，功耗延时积(PDP)平均降低了46.0%，晶体管数目平均减少了9.1%。
- 软错误 /
- 单粒子翻转 /
- 单粒子瞬态 /
- 加固锁存器
Abstract: To reduce the soft error rate of the circuit, this paper proposes a low power soft error tolerant latch based on time redundancy technology. The proposed latch can fully tolerate the Single Event Upset (SEU) when particles strike on internal nodes. Furthermore, it can efficiently mask the input Single Event Transient (SET). Its output node will not enter a high impedance state when a particle strikes on internal nodes, so the proposed latch can be applied to clock-gating circuits. Detailed SPICE simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures. Compared with other soft error tolerant latches, the proposed latch introduces 13.4% delay overhead on average. While it can achieve 44.3% increase in filterable SET pulse width, 48.5% reduction in power, 46.0% reduction in Power Delay Product (PDP), and 9.1% reduction in transistor numbers on average.
- Soft error /
- Single Event Upset (SEU) /
- Single Event Transient (SET) /
- Hardened latch

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参考文献(26)

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