高性能集成锁相环中低失配电荷泵的设计

施展; 余隽; 唐祯安; 蔡泓; 冯冲

doi:10.11999/JEIT160826

高性能集成锁相环中低失配电荷泵的设计

doi: 10.11999/JEIT160826

施展¹,
余隽¹,
唐祯安¹,
蔡泓¹,
冯冲²

1.
(大连理工大学电子科学与技术学院大连 116024) ②(大连民族大学信息与通信工程学院大连 116600

基金项目:

国家自然科学基金(61131004, 61274076, 61001054)

计量
- 文章访问数: 1428
- HTML全文浏览量: 155
- PDF下载量: 342
- 被引次数: 0
出版历程
- 收稿日期: 2016-08-03
- 修回日期: 2017-02-08
- 刊出日期: 2017-06-19

Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops

1.
(School of Electronic Science and Technology, Dalian University of Technology, Dalian 116024, China)

Funds:

The National Natural Science Foundation of China (61131004, 61274076, 61001054)

摘要

摘要: 在分析电荷泵结构、工作原理和产生杂散机理的基础上，该文提出了一种低静态电流失配、低时序失配的高性能电荷泵。此电荷泵通过减小电荷泵开关过程中时序失配和电流失配，减小了高频锁相环中的抖动和杂散。基于中芯国际0.18 m CMOS射频工艺技术和1.8 V电源电压，对采用此高性能电荷泵的锁相环进行了相位噪声仿真。仿真结果验证了这些锁相环具有低噪声特性：在480 MHz的输出频率下，二阶锁相环的周期抖动为1.05 ps，最大参考杂散为-121 dBc。
- 集成电路 /
- 锁相环 /
- 抖动 /
- 参考杂散
Abstract: On the basis of the analysis of the structure, operation principle and mechanism of generating spurs of the charge pump, a charge pump with a low static current mismatch and a low timing mismatch is proposed. This charge pump suppresses the jitter and spurs in high-speed Phase-Looked Loops (PLL) by improving the timing mismatch and the current mismatch during switching in the charge pump. Based on the SMIC 0.18 m CMOS radio frequency technology with 1.8 V power supply, the phase noise simulation of the PLLs adopting the proposed charge pump is performed. The simulation results demonstrate that those PLLs achieve a low noise performance: the second-order PLL shows a period jitter of 1.05 ps and the largest reference spur of -121 dBc with the PLL output frequency of 480 MHz.
- Integrated Circuits (IC) /
- Phase-Locked Loop (PLL) /
- Jitter /
- Reference spur

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参考文献(31)

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