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可重构非线性布尔函数利用率模型研究与硬件设计

戴紫彬 王周闯 李伟 李嘉敏 南龙梅

戴紫彬, 王周闯, 李伟, 李嘉敏, 南龙梅. 可重构非线性布尔函数利用率模型研究与硬件设计[J]. 电子与信息学报, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733
引用本文: 戴紫彬, 王周闯, 李伟, 李嘉敏, 南龙梅. 可重构非线性布尔函数利用率模型研究与硬件设计[J]. 电子与信息学报, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733
DAI Zibin, WANG Zhouchuang, LI Wei, LI Jiamin, Nan Longmei. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. Journal of Electronics & Information Technology, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733
Citation: DAI Zibin, WANG Zhouchuang, LI Wei, LI Jiamin, Nan Longmei. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. Journal of Electronics & Information Technology, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733

可重构非线性布尔函数利用率模型研究与硬件设计

doi: 10.11999/JEIT160733
基金项目: 

国家自然科学基金(61404175)

Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function

Funds: 

The National Natural Science Foundation of China (61404175)

  • 摘要: 为解决序列密码中非线性布尔函数(Non-Linear Boolean Function, NLBF)硬件资源利用率低的问题,该文对以查找表(Look-Up Table, LUT)为基本构件的利用率模型进行研究,并结合适配算法的前期处理结果确定影响硬件利用率的3个基本参数(LUT大小、单元规模和输入端口数目);在此基础上,以变量频次为约束实现NLBF的映射,完成非线性运算单元的设计,单元支持多路并行处理。在SMIC 180 nm下进行逻辑综合,并行度为32时,工作频率达到241 MHz,吞吐率为7.71 Gb/s;对不同NLBF进行利用率评估,利用率均达到91.14%以上,并且随着并行度增加,利用率不断增大。
  • ZENG G, DONG X, and BORNEMANN J. Reconfigurable feedback shift register based stream cipher for wireless sensor networks[J]. IEEE Wireless Communications Letters, 2013, 2(5): 559-562. doi: 10.1109/wcl.2013.13.130292.
    禹思敏, 吕金虎, 李澄清. 混沌密码及其在保密通信中应用的进展[J]. 电子与信息学报, 2016, 38(3): 735-752. doi: 10.11999 /JEIT151356.
    YU Simin, LU Jinhu, and LI Chengqing. Some progresses of chaotic cipher and its application in multimedia secure communications[J]. Journal of Electranics Information Technology, 2016, 38(3): 735-752. doi: 10.11999/JEIT151356.
    丁群, 彭喜元, 杨自恒. 基于神经网络算法的组合序列密码芯片[J]. 电子学报, 2006, 34(3): 409-412. doi: 10.3321/j.issn: 0372-2112.2006.03.006.
    DING Qun, PENG Xiyuan, and YANG Ziheng. The cipher chip of combining stream based on the neural network algorithm[J]. Acta Electronica Sinica, 2006, 34(3): 409-412. doi: 10.3321/j.issn:0372-2112.2006.03.006.
    MIKE H and JAY S. Improving FPGA performance and area using an adaptive logic module[J]. Leuven Belgium, Spring Berlin Heidelberg, 2004, 32(03): 135-144. doi: 10.1007/ 978-3-540-30117-2_16.
    ANDERSON J H and QIANG W. Area-efficient FPGA logic elements: Architecture and synthesis[C]. 16th Asia and South Pacific Design Automation Conference, Yokohama, 2011: 369-375. doi: 10.1109/aspdac.2011.5722215.
    陈韬, 杨萱, 戴紫彬, 等. 面向序列密码的非线性反馈移位寄存器可重构并行化设计[J]. 上海交通大学学报, 2013, 47(1): 28-32.
    CHEN Tao, YANG Xuan, DAI Zibin, et al. Design of a reconfigurable parallel nonlinear feedback shift register structure targeted at stream cipher[J]. Journal of Shanghai Jiao Tong University, 2013, 47(1): 28-32.
    SATWANT S, JONATHAN R, PAUL C, et al. The effect of logic block architecture on FPGA performance[J]. IEEE Journal of Solid-State Circuits, 1992, 27(3): 281-287. doi: 10.1109/4.121549.
    ELIAS A and JONATHAN R. The effect of LUT and cluster size on deep-submicron FPGA performance and density[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(3): 288-298. doi: 10.1109/tvlsi.2004. 824300.
    KUON L and JONATHAN R. Measuring the gap between FPGAs and ASICs[C]. Acm/sigda International Symposium on Field Programmable Gate Arrays, Monterey, 2015: 21-30. doi: 10.1145/1116201.1117205.
    MANA P, TALATI N, RISWADKAR A, et al. Stateful-NOR based reconfigurable architecture for logic implementation[J]. Microelectronics Journal, 2015, 46(6): 551-562. doi: 10.1016/ j.mejo.2015.03.021.
    TANG X and WANG L. The effect of LUT size on nanometer FPGA architecture[C]. IEEE 11th International on Solid-State and Integrated Circuit Technology, Xian, 2012: 1-4. doi: 10.1109/icsict.2012.6467767.
    DICKIN D and SHANNON L. Exploring FPGA technology mapping for fracturable LUT minimization[C]. International Conference on Field-Programmable Technology, New Delhi, 2011: 1-8. doi: 10.1109/fpt.2011.6132691.
    FAROOQ U and ASLAM M. Design and implementation of basic building blocks of FPGA using memristor-transistor hybrid approach[C]. 2015 Fifth International Conference on Innovative Computing Technology, Vigo, 2015: 142-147. doi: 10.1109/intch.2015.7173484.
    ASLAM M H, FAROOQ U, AWAIS M, et al. Exploring the effect of LUT size on the area and power consumption of a novel memristor-transistor hybrid FPGA architecture[J]. Arabian Journal for Science Engineering, 2016, 41(8): 3035-3049. doi: 10.1007/s13369-016-2068-8.
    TANG Xifan and DE-MICHELI G. Pattern-based FPGA logic block and clustering algorithm[P]. US, 20160063168. 2016. doi: 10.1109/fpl.2014.6927429.
    SAXENA S and TIWARI A. A comparative study of leakage reduction techniques used in, FGPA for optimized area and power consumption[J]. International Journal of Engineering Research Applications, 2014, 4(2): 89-94.
    王周闯, 戴紫彬, 李伟. 高效适配NLBF序列密码的全局定向搜索算法[J]. 计算机应用, 2016, 36(9): 65-69. doi: 10.11772/ j.issn 1001-9081.2016.09.
    WANG Zhouchuang, DAI Zibin, and LI Wei. Global directional search algorithm adapting NLBF sequence cryptogram efficiently[J]. Journal of Computer Applications, 2016, 36(9): 65-69. doi: 10.11772/j.issn 1001-9081.2016.09.
    秦晓懿, 王瀚晟, 曾烈光. 线性和非线性寄存器系统的并行化技术[J]. 电子学报, 2003, 31(3): 406-410. doi: 10.3321/j.issn: 0372-2112.2003.03.023.
    QIN Xiaoyi, WANG Hansheng, and ZENG Lieguang. Paralleling techniques for linear and nonlinear register systems[J]. Acta Electronica Sinica, 2003, 31(3): 406-410. doi: 10.3321/j.issn:0372-2112.2003.03.023.
    李伟. 面向序列密码的反馈移位寄存器可重构并行化设计技术研究[D]. [硕士论文], 解放军信息工程大学, 2009.
    LI Wei. Research on technology of reconfigurable parallel feedback shift register targeted at stream cipher[D]. [Master dissertation], PLA Information Engineering University, 2009.
    REBEIRO C and MUKHOPADHYAY D. High speed compact elliptic curve cryptoprocessor for FPGA platforms [C]. International Conference Progress in Cryptology- Indocrypt 2008, Kharagpur, 2008: 376-388. doi: 10.1007/978- 3-540-89754-5_29.
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出版历程
  • 收稿日期:  2016-07-08
  • 修回日期:  2016-12-12
  • 刊出日期:  2017-05-19

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