高效低功耗低并行度LDPC编码方法

燕威; 薛长斌

doi:10.11999/JEIT151362

高效低功耗低并行度LDPC编码方法

doi: 10.11999/JEIT151362

燕威¹,
薛长斌¹

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- 被引次数: 0
出版历程
- 收稿日期: 2015-12-03
- 修回日期: 2016-05-10
- 刊出日期: 2016-09-19

An Efficient LDPC Encoder Scheme with Low-power Low-parallel

YAN Wei¹,
XUE Changbin¹

摘要

摘要: 低密度奇偶校验码(LDPC)是最接近香农极限的纠错码之一，具有优良的性能且被国际通信标准组织广泛采纳为信道编码。CCSDS推荐使用LDPC码作为近地空间和深空探测的信道编码方案。该文提出高效，低功耗，低并行度的LDPC编码方法。该方法通过采用插0和改变循环矩阵的结构实现了对CCSDS标准中推荐的校验矩阵子矩阵大小为奇数的LDPC码的低并行度编码。通过分析编码过程，提出了只对输入信息中的1有效信息位进行编码的方案，减少了编码中移位寄存器的移位次数，大幅度地降低了编码器功耗。文中采用FPGA实现了(8176, 7154)78LDPC码的编码器，结果显示在硬件开销略有增加的情况下，编码功耗大幅度下降，编码速率接近低并行度编码方案。
- 差错控制编码 /
- 低并行度 /
- 低功耗 /
- QC-LDPC /
- VLSI设计
Abstract: Low-density parity-check code is the one of error-correction codes most approaching Shannon limit, which is adopted as a standard for channel coding by many international communication standard organizations. CCSDS recommends LDPC as channel coding scheme in near earth space and deep space communication. An efficient LDPC coding scheme with low power and low parallel is presented in this paper. By filling 0 and changing the cyclic-matrix structure, the proposed scheme implements a low parallel coding for the LDPC, which is recommended by CCSDS, and of which the size of submatrix of check matrices is odd. By analyzing the coding process, the valid bit 1 among input information bits is coded only, and it decreases obviously the code power. The encoder architecture for 7/8 LDPC is implemented in FPGA. The result shows that encoder achieves a high encoding speed approaching low parallel encoder scheme and a much lower encoding power while increases few hardware overhead.
- Error-correction codes /
- Low parallel /
- Low power /
- QC-LDPC /
- VLSI design

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参考文献(21)

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