面向DVB-S2标准LDPC码的高效编码结构

兰亚柱; 杨海钢; 林郁

doi:10.11999/JEIT151198

面向DVB-S2标准LDPC码的高效编码结构

doi: 10.11999/JEIT151198

2.
(中国科学院电子学研究所可编程芯片与系统研究室北京 100190) ②(中国科学院大学北京 100049)

基金项目:

国家自然科学基金(61404140, 61271149, 61106033)

计量
- 文章访问数: 1711
- HTML全文浏览量: 153
- PDF下载量: 424
- 被引次数: 0
出版历程
- 收稿日期: 2015-10-29
- 修回日期: 2016-03-15
- 刊出日期: 2016-07-19

Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard

2.
(System of Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds:

The National Natural Science Foundation of China (61404140, 61271149, 61106033)

摘要

摘要: 面向DVB-S2标准LDPC码，该文旨在实现一种基于FPGA的高效编码结构，提出一种快速流水线并向递归编码算法，可以显著提高编码数据信息吞吐率。同时，通过并向移位运算和并向异或运算的处理结构计算编码中间变量及校验位信息，在提高编码并行度的同时可有效减少存储资源的消耗。此外，针对动态自适应编码的情况优化了LDPC码编码存储结构，有效复用了数据存储单元和RAM地址发生器，进一步提高FPGA的硬件逻辑资源利用率。针对DVB-S2标准LDPC码，基于Stratix IV系列FPGA的验证结果表明，所提编码结构在系统时钟为126.17 MHz时，编码数据信息吞吐率达20 Gbps以上。
- LDPC码 /
- 编码结构 /
- DVB-S2标准 /
- FPGA
Abstract: For DVB-S2 standard LDPC code, to achieve an efficient encoding architecture based on FPGA, a fast pipeline parallel and recursive encoding algorithm is proposed which can significantly improve encoding speed and improve the encoding data rate of information throughput. At the same time, the parallel shift operation and parallel XOR processing structure is introduced to calculate code intermediate variable. It can effectively improve the encoding parallel degree and reduce the occupancy volume of storage resources. In addition, according to dynamic adaptive encoding, the storage structure and effective reuse of data storage unit and the RAM address generator are optimized. In this case, the utilization of FPGA resources is further improved. The experiment based on Stratix IV series FPGA for DVB-S2 standard LDPC code, shows that the proposed method can achieve system clock frequency of 126.17 MHz and encoding data rate of information throughput of more than 20 Gbps.
- LDPC code /
- Encoding architecture /
- DVB-S2 standard /
- FPGA

HTML全文

参考文献(22)

DVB Orgamzation. ETSI EN 302 307 V1. 2. 1. Digital video broadcasting (DVB); second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broadband satellite appiications (DVB-S2)[S]. 2009.

GALLAGER R G. Low density parity check codes[J]. IRE Transactions on Information Theory, 1962, 8(1): 21-28.

MACKAY D J C and NEAL R M. Near Shannon limit performance of low-density parity check codes[J]. Electronics Letters, 1996, 32(18): 1645-1646.

LEE Youngjoo, JAEHWAN J, and IN-CHEOL P. Energy- scalable 4KB LDPC decoding architecture for NAND-Flash- Based storage systems[J]. IEICE Transactions on Electronics, 2016, 99(2): 293-301.

WANG J, CHE S, LI Y, et al. Optimal design of joint network LDPC codes over orthogonal multiple-access relay channels [J]. International Journal of Grid and Utility Computing, 2016, 7(1): 68-74.

郭锐, 刘春于, 张华, 等. 分簇无线传感器网络中根校验全分集LDPC码设计与能效分析[J]. 电子与信息学报, 2015, 37(7): 1580-1585. doi: 10.11999/JEIT141294.

GUO Rui, LIU Chunyu, ZHANG Hua, et al. Full diversity LDPC codes design and energy efficiency analysis for clustering wireless sensor networks[J]. Journal of Electronics Information Technology, 2015, 37(7): 1580-1585. doi: 10. 11999/JEIT141294.

ZHAO W H and LONG J P. Implementing the NASA deep space LDPC codes for defense applications[C]. 2013 IEEE, Military Communications Conference. San Diego, CA, USA, IEEE, 2013: 803-808.

张小平, 赵艳杰. DVB-S2技术的创新性分析[J]. 有线电视技术, 2014, (2): 17-20.

ZHANG Xiaoping and ZHAO Yanjie. Innovative analysis of DVB-S2 technology[J]. Cable TV Technology, 2014, (2): 17-20.

陈豪威, 王秀敏. 基于DVB-S2标准的LDPC码编译码器设计研究[J]. 电视技术, 2012, 36(3): 1-3.

CHEN Haowei and WANG Xiumin. Study on design of LDPC encoder and decoder for DVB-S2[J]. Video Engineering, 2012, 36(3): 1-3.

范光荣, 王华. 基于DVB-S2的高速多码率LDPC编码器的FPGA设计与实现[J]. 北京理工大学学报, 2008, 28(9): 813-816.

FAN Guangrong and WANG Hua. FPGA design and implementation of high speed multi-rate LDPC encoder based on DVB-S2[J]. Transactions of Beijing Institute of Technology, 2008, 28(9): 813-816.

华力, 雍玲, 雷菁. 基于FPGA的DVB-S2通用LDPC编码器设计与实现[J]. 通信技术, 2008, 41(1): 12-14.

HUA Li, YONG Ling, and LEI Qing. Design and implementation of universal LDPC code encoder in the DVB-S2 based on FPGA[J]. Communications Technology, 2008, 41(1): 12-14.

闫国强, 王勇. 基于DVB-S2的通用LDPC编码器的FPGA 设计[J]. 电视技术, 2013, 37(1): 1-3.

YAN Guoqiang and WANG Yong. Design and implementation of universal LDPC code encoder in the DVB-S2 based on FPGA[J].Video Engineering, 2013, 37(1): 1-3.

LEE I K, KIM M H, OH D G, et al.. High-speed LDPC encoder architecture for digital video broadcasting systems [C]. 2013 IEEE, International Conference on ICT Convergence (ICTC). Jeju Island, South Korea, IEEE, 2013: 606-607.

GOMES M, FALCAO G, SENGO A, et al.. High throughput encoder architecture for DVB-S2 LDPC-IRA codes[C]. ICM 2007 IEEE Internatonal Conference on Microelectronics. Cairo, Egypt, IEEE, 2007: 271-274.

兰亚柱, 杨海钢, 林郁. 动态自适应低密度奇偶校验码译码器的FPGA实现[J]. 电子与信息学报, 2015, 37(8): 1937-1943. doi: 10.11999/JEIT141609.

LAN Yazhu, YANG Haigang, and LIN Yu. Design of dynamic adaptive LDPC decoder based on FPGA[J]. Journal of Electronics Information Technology, 2015, 37(8): 1937-1943. doi: 10.11999/JEIT141609.

施引文献

资源附件(0)

访问统计