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数据锁存处理的低误码率编码方法研究

吴金 江琦 郑丽霞 孙东辰 宋科 孙伟锋

吴金, 江琦, 郑丽霞, 孙东辰, 宋科, 孙伟锋. 数据锁存处理的低误码率编码方法研究[J]. 电子与信息学报, 2016, 38(7): 1831-1837. doi: 10.11999/JEIT151104
引用本文: 吴金, 江琦, 郑丽霞, 孙东辰, 宋科, 孙伟锋. 数据锁存处理的低误码率编码方法研究[J]. 电子与信息学报, 2016, 38(7): 1831-1837. doi: 10.11999/JEIT151104
WU Jin, JIANG Qi, ZHENG Lixia, SUN Dongchen, SONG Ke, SUN Weifeng. Research on Low Bit Error Rate Encoding Method for Data Latch Processing[J]. Journal of Electronics & Information Technology, 2016, 38(7): 1831-1837. doi: 10.11999/JEIT151104
Citation: WU Jin, JIANG Qi, ZHENG Lixia, SUN Dongchen, SONG Ke, SUN Weifeng. Research on Low Bit Error Rate Encoding Method for Data Latch Processing[J]. Journal of Electronics & Information Technology, 2016, 38(7): 1831-1837. doi: 10.11999/JEIT151104

数据锁存处理的低误码率编码方法研究

doi: 10.11999/JEIT151104
基金项目: 

江苏省自然科学基金(BK2012559)

Research on Low Bit Error Rate Encoding Method for Data Latch Processing

Funds: 

Natural Science Foundation of Jiangsu Province (BK2012559)

  • 摘要: 对于时间信号量化后的数字编码处理,传统编码方法高频条件下存在高误码率导致数据量化精度退化的问题。该文从数据误码根源分析入手,建立起不同状态模式下包含锁存和延迟失配效应的误码解析分析模型,并在二进制和格雷码编码方法对比的基础上,分析了低误码率的同频码编码设计方法。基于TSMC 0.35 ?m CMOS工艺,完成了采用同频码编码方法的时间数字转换器(TDC)电路及其版图设计,多项目晶元(MPW)芯片的测试结果表明:同频编码的误码率相比同等条件下传统编码方法的误码率明显降低,并与理论分析基本吻合。
  • LI Qianfeng and HU Qingsheng. A 10ps 500MS/s two-channel Vernier TDC in 0.18 CMOS technology[C]. IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA), Ottawa, Canada, 2014: 1268-1271. doi: 10.1109/WARTIA.2014.6976513.
    BREZINA C, FU Y, ZAPPON F, et al. GOSSIPO-4: evaluation of a Novel PLL-based TDC-technique for the readout of gridpix-detectors[J]. IEEE Transactions on Nuclear Science, 2014, 61(2): 1007-1014. doi: 10.1109/ TNS.2014.2301141.
    UCHIDA Daisuke, IKEBE Masayuki, MOTOHISA Junichi, et al. A 12-bit, 5.5-W single-slope ADC using intermittent working TDC with multi-phase clock signals[C]. International Conference on Electronics, Circuits and Systems (ICECS), Marseille, France, 2014: 770-773. doi: 10.1109/ICECS. 2014.7050099.
    KALISZ J, SZPLET R, PELKA R, et al. Single-chip interpolating time counter with 200-ps resolution and 43-s range[J]. IEEE Transactions on Instrumentation and Measurement, 1997, 46(4): 851-856. doi: 10.1109/19.650787.
    KATOH Kentaroh, DOI Yoshihito, ITO Satoshi, et al. An analysis of stochastic self-calibration of TDC using two ring oscillators[C]. IEEE Conference on Asian Test Symposium (ATS), Jiaosi Township, China, 2013: 140-146. doi: 10.1109/ ATS.2013.35.
    URANO Yuki, YUN WonJoo J, KURODA Tadahiro, et al. A 1.26 mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL[C]. International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013: 1576-1579. doi: 10.1109/ISCAS.2013.6572161.
    姚茂群, 张立彬, 耿亮. 电流型 CMOS 脉冲 D 触发器设计[J]. 电子与信息学报, 2014, 36(9): 2278-2282. doi: 10.3724/ SP.J.1146.2013.00343.
    YAO Maoqun, ZHAGN Libin, and GENG Liang. Design of current-mode CMOS pulse-triggered D flip-flops[J]. Journal of Electronics Information Technology, 2014, 36(9): 2278- 2282. doi: 10.3724/SP.J.1146.2013.00343.
    欧庆于, 罗芳, 吴晓平. 基于 NCL 电路的抗故障攻击设计研究[J]. 电子与信息学报, 2014, 36(7): 1648-1655. doi: 10.3724/ SP.J.1146.2013.00750.
    OU Qingyu, LUO Fang, and WU Xiaoping. The research on countermeasure against fault attacks for NCL circuits[J]. Journal of Electronics Information Technology, 2014, 36(7): 1648-1655. doi: 10.3724/SP.J.1146.2013.00750.
    PELKA R, KALISZ J, and SZPLET R. Nonlinearity correction of the integrated time-to-digital converter with direct coding[J]. IEEE Transactions on Instrumentation and Measurement, 1997, 46(2): 449-453. doi: 10.1109/19.571882.
    POLAT and MANZAK A. Design and analysis of low power Carbon Nanotube Field Effect Transistor (CNFET) D Flip-Flops (DFFs)[C]. International Conference on Computer Research and Development (ICCRD), Shanghai, China, 2011, 3: 399-401. doi: 10.1109/ICCRD.2011.5764223.
    TAIT A N and PRUCNAL P R. Applications of wavelength-fan-in for high-performance distributed processing systems[C]. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, Paris, France, 2014: 177-178. doi: 10.1109/NANOARCH.2014. 6880485.
    JIN Wei, LU Sheng, HE Weifeng, et al. Robust design of sub-threshold flip-flop cells for wireless sensor network[C]. International Conference on VLSI and System-on-Chip (VLSI-SoC), Hong Kong, China, 2011: 440-443. doi: 10.1109/VLSISoC.2011.6081623.
    SALIGRAM Rakshith and RAKSHITH T R. Contemplation of synchronous Gray Code counter and its variants using reversible logic gates[C]. IEEE Conference on Information Communication Technologies (ICT), JeJu Island, Korea, 2013: 661-665. doi: 10.1109/CICT.2013.6558177.
    KALISZ J, PAWLOWSKI M, and PELKA R. Error analysis and design of the Nutt time-interval digitiser with picosecond resolution[J]. Journal of Physics E: Scientific Instruments, 1987, 20(11): 1330-1341.
    REDANT Tom, STUBBE Frederic, and DEHAENE Wim. A low power time-of-arrival ranging front end based on a 8-channel 2.2 mW, 53ps single-shot-precision time-to-digital converter[C]. IEEE Conference on Solid State Circuits, Jeju, Korea, 2011: 321-324. doi: 10.1109/ASSCC.2011.6123578.
    HENZLER Stephan. Time-to-Digital Converters[M]. London, Springer Science Business Media, 2010: 25-31.
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出版历程
  • 收稿日期:  2015-09-29
  • 修回日期:  2016-03-03
  • 刊出日期:  2016-07-19

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