动态自适应低密度奇偶校验码译码器的FPGA实现

兰亚柱; 杨海钢; 林郁

doi:10.11999/JEIT141609

动态自适应低密度奇偶校验码译码器的FPGA实现

doi: 10.11999/JEIT141609

2.
(中国科学院电子学研究所可编程芯片与系统研究室北京 100190) ②(中国科学院大学北京 100086)

基金项目:

国家自然科学基金(61404140, 61271149, 61106033)

计量
- 文章访问数: 1697
- HTML全文浏览量: 128
- PDF下载量: 712
- 被引次数: 0
出版历程
- 收稿日期: 2014-12-15
- 修回日期: 2015-02-15
- 刊出日期: 2015-08-19

Design of Dynamic Adaptive LDPC Decoder Based on FPGA

2.
(System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

摘要

摘要: 在复杂深空通信环境中，自适应能力的强弱对低密度奇偶校验(LDPC)码译码器能否保持长期稳定工作具有重要影响。该文通过对DVB-S2标准LDPC码译码器各功能模块的IP化设计，将动态自适应理论参数化映射到各功能模块中，实现动态自适应LDPC码译码器的设计。基于Stratix IV系列FPGA的验证结果表明，动态自适应LDPC译码器可以满足不同码率码长及不同性能需求下的译码。同时，单译码通道可以保证译码数据信息吞吐率达到40.9~71.7 Mbps。
- LDPC码译码器 /
- 动态自适应 /
- DVB-S2标准 /
- FPGA
Abstract: Faced with the complex environment of deep space communication, the adaptive capacity can have an impact on the ability of the Low Density Parity Check (LDPC) code decoder to maintain long-term stability. This paper proposes a design method of dynamic adaptive LDPC code decoder. Through the IP-based design of each function module, the design method of dynamic adaptive can be mapped to each function module in DVB-S2 LDPC code decoder. The verification results based on the Stratix IV FPGA show the dynamic adaptive LDPC code decoder not only can decode under the different code length and code rate, but also can decode under the different decoding performance. Meanwhile, the single-channel decoder can ensure the information throughput to reach to 40.9~71.7 Mbps.
- Low Density Parity Check (LDPC) code decoder /
- Dynamic adaptive /
- DVB-S2 standard /
- FPGA

HTML全文

参考文献(27)

Gallager R G. Low density parity check codes[J]. IRE Transactions on Information Theory, 1962, 8(1): 21-28.

Mackay D J C and Neal R M. Near Shannon limit performance of low-density parity check codes[J]. Electronics Letters, 1996, 32(18): 1645-1646.

陈豪威, 王秀敏. 基于DVB-S2标准的LDPC码编译码器设计研究[J].电视技术, 2012, 36(3): 1-3.

Chen Hao-wei and Wang Xiu-min. Study on design of LDPC encoder and decoder for DVB-S2[J]. Video Engineering, 2012, 36(3): 1-3.

江桂芳, 彭克荣. 基于FPGA的高速并行DVB-S2标准LDPC译码[J]. 空间电子技术, 2013, 10(1): 58-61, 95.

Jiang Gui-fang and Peng Ke-rong. A FPGA-dased high-speed paraller LDPC decoder for DVB-S2 system[J]. Space Electronic Technology, 2013, 10(1): 58-61, 95.

Kienle F, Brack T, and Wehn N. A synthesizable IP core for DVB-S2 LDPC code decoding[C]. Proceedings of the Design, Automation and Test in Europe conference, Munich Germany, 2005: 100-105.

Gomes M, Falc?o G, Silva V, et al.. Flexible parallel architecture for DVB-S2 LDPC decoders[C]. Proceedings of the Global Telecommunications Conference, Washington, DC, USA, 2007: 3265-3269.

张高远, 周亮, 苏伟伟, 等. 基于平均幅度的 LDPC 码加权比特翻转译码算法[J]. 电子与信息学报, 2013, 35(11): 2572-2578.

Zhang Gao-yuan, Zhou Liang, Su Wei-wei, et al.. Average magnitude based weighted bit-flipping decoding algorithm for LDPC codes[J]. Journal of Electronics Information Technology, 2013, 35(11): 2572-2578.

孙锦华, 刘鹏, 吴小钧. 联合旋转平均周期图和解调软信息的载波同步方法[J]. 电子与信息学报, 2013, 35(9): 2200-2205.

Sun Jin-hua, Liu Peng, and Wu Xiao-jun. A joint rotational periodogram averaging and demodulation soft information carrier synchronization algorithm[J]. Journal of Electronics Information Technology, 2013, 35(9): 2200-2205.

钟州, 金梁, 黄开枝, 等. 基于二维信息修正减小LDPC码安全间隙的译码算法[J]. 电子与信息学报, 2013, 35(8): 1946-1951.

Zhong Zhou, Jin Liang, Huang Kai-zhi, et al.. Decoding algorithm for reducing security gap of LDPC codes based on two-dimensional information correction[J]. Journal of Electronics Information Technology, 2013, 35(8): 1946-1951.

Roberts M K and Jayabalan R. A modified optimally quantized offset min-sum decoding algorithm for low- complexity LDPC decoder[J]. Wireless Personal Communications, 2014, 80(2): 1-10.

倪俊枫, 甘小莺, 张海滨, 等. 改进的分层修正最小和LDPC译码算法及译码器设计[J]. 系统工程与电子技术, 2008, 30(12): 2531-2535.

Ni Jun-feng, Gan Xiao-ying, Zhang Hai-bin, et al.. Improved layered modified minimal sun LDPC decoding algorithm and LDPC decoder design[J]. Systems Engineering and Electronics, 2008, 30(12): 2531-2535.

管武, 乔华, 董明科, 等. 多码率LDPC码高速译码器的设计与实现[J]. 电路与系统学报, 2009, 14(2): 1-6.

Guan Wu, Qiao Hua, Dong Ming-ke, et al.. Design and implementation of a high-throughput decoder for multi-rate LDPC code[J]. Journal of Circuits and Systems, 2009, 14(2): 1-6.

赵旦峰, 赵辉, 许元志, 等. 可配置LDPC码译码器的FPGA设计与实现[J]. 黑龙江大学自然科学学报, 2012, 29(2): 259-264.

Zhao Dan-feng, Zhao Hui, Xu Yuan-zhi, et al.. Design and implementation of configurable LDPC decoder based on FPGA[J]. Journal of Natural Science of Heilongjiang University, 2012, 29(2): 259-264.

唐凯林, 杜慧敏, 段高攀, 等. 多码率、多码长LDPC译码器的设计与实现[J]. 电子技术应用, 2013, 39(12): 58-60.

Tang Kai-lin, Du Hui-min, Duan Gao-pan, et al.. Design and implementation of multi-rate and multi-length LDPC decoder[J]. Application of Electronic Technique, 2013, 39(12): 58-60.

林梅英, 许肖梅, 陈友淦, 等. 码率兼容QC-LDPC码在水声通信中的应用[J]. 声学技术, 2014, 15(5): 460-463.

Lin Mei-ying, Xu Xiao-mei, Chen You-gan, et al.. Applications of rate-compatible QC-LDPC codes in underwater acoustic communication[J]. Technical Acoustics, 2014, 15(5): 460-463.

栾志斌, 裴玉奎, 葛宁, 等. 低存储高速可重构LDPC码译码器设计及ASIC实现[J]. 电子与信息学报, 2014, 36(10): 2287-2292.

Luan Zhi-bin, Pei Yu-kui, Ge Ning, et al.. Design and ASIC implementation of low memory high throughput reconfigurable LDPC decoder[J]. Journal of Electronics Information Technology, 2014, 36(10): 2287-2292.

施引文献

资源附件(0)

访问统计