低功耗Clock-Gating技术在SAR实时成像处理中的应用
Low Power Clock-Gating Method and Its Applications in SAR Real-Time Processor
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摘要: 功耗问题在SAR实时成像系统中是不容忽视的。该文以实时成像系统中的输入分机为研究平台,测试了信号处理中常用芯片DSP,SBSRM,FPGA在采用Clock-gating技术前后,功耗的变化。通过大量的实验结果,验证了Clock-gating技术在SAR实时信号处理中的可行性,对降低SAR实时成像系统,尤其是星载实时成像系统的功耗有一定的指导意义。Abstract: Power consumption has to be taken into consideration in an applied SAR real-time processor. The power consumption is measured before and after clock-gating method had been applied to DSP, SBSRAM and FPGA of an air-borne SAR real-time preprocessor board respectively by software. It has been proved that clock-gating method is feasible for low power design in the SAR especially the future space-borne SAR real-time processor.
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Albonesi D H. An architectural and circuit-level approach to improving the energy efficiency of microprocessor memory structures, 10th International Conference on VLSI (VLSI99),Hyderabad, India, December 1999:192 - 205.[2]Su C, Despain A. Cache design trade-offs for power and performance optimization: A case study. In IEEE Symposium on Low Power Electronics, California, United States, 1995:63 - 68.Shimazakietal Y. An automatic-power-save cache memory for Iow-power RISC processors. In IEEE Symposium on Low Power Electronics, Monterey, California, United States, 1995:58 - 59.[3]陈冰冰.SAR实时信号预处理和高分辨率实时成像系统的研究.[博士论文],北京:中国科学院电子学研究所,2002年3月.[4]Borah M, Owens R M, Irwin M J. High-throughput and low power DSP using clocked-CMOS circuitry. In Int. Symposium on Low Power Design, Dana Point, California, United States, April 1995: 139- 144.[5]Benini L, Siegel P, de Micheli G. Saving power by synthesizing gated clocks for sequential circuits. IEEE Design Test of Computers, Winter 1994:32 - 41.[6]任丽香, 等. TMS320C6000 系列 DSPS 的原理与应用. 北京:电子工业出版社, 2000:144 - 145. -
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