宽带数字下变频的一种高效实现结构
An Efficient Implementation Architecture for Wideband Digital Downconversion
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摘要: 宽带数字接收系统要以大的调谐带宽截获窄带信号,要求数字下变频器具有高的数据率和快的调谐时间,现有的商用数字下变频器不能满足这些要求。本文提出一种高效实现结构,综合利用DFT滤波器的灵活性和多相滤波的高效性,按照先抽取数据,再低通滤波、混频的顺序,较好地解决了硬件速度和高速数据流不匹配的问题。计算机模拟结果证明了处理结构的有效性。
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关键词:
- 数字下变频; 宽带数字接收; 多相滤波
Abstract: The wideband digital receiver systems require DDC with high speed and short tuning time in order to intercept narrowband signal in broad tuning bandwidth. However, these requirements can not be met by the commercial DDC. In this paper an efHcient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution of the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture. -
宗孔德,多抽样率信号处理,北京,清华大学出版社,1996年7月,47-50.[2]J. Fudge, M. Legako, C. Sehreiner, An approach to efficient wideband digital downconversion, Proc. ICSPAT, Toronto, Canada, 1998, 713-717.[3]R.G. Vaughan, N. L. Scott, D. R. White, The theory of bandpass sampling, IEEE Trans. on SP, 1991, SP-39(9), 1973-1984.[4]D.R. Zahirniak, D. L. Sharpin, T. W. Fields, A hardware-efficient multirate digital channelized receiver architecture, IEEE Trans. on AES, 1998, AES-34(1), 137-151.[5]R. Baines, The DSP bottleneck, IEEE Communications Magazine, 1995, 33(5), 46-54. -
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