Abstract: Interconnection network plays an important role in Coarse-Grained Reconfigurable Arrays (CGRAs), and it has a significant influence on the performance, area cost and power consumption. To reduce the area cost and power consumption caused by the interconnection network, and improve the performance of CGRA, a self-routing and non-blocking interconnection network is proposed, and a hierarchical network topology is constructed. Through the proposed interconnection network, connection and data exchange can be established between any pair of processing elements. Moreover, the process of connection establishment is self-routing and non-blocking. Experimental results demonstrate that, compared with existing CGRAs, the overall performance of the proposed architecture is improved up to 46.2% at the expense of 14.1% increase of area cost.