Hardware-efficient Parallel Structures for Linear-phase FIR Digital Filter Based on Iterated Short Convolution Algorithm
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摘要: 该文基于快速卷积算法，提出一种适用于线性相位FIR滤波器的并行结构。该结构采用快速卷积算法减少子滤波器个数，同时让尽可能多的子滤波器具有对称系数，然后利用系数对称的特性减少子滤波器模块中的乘法器数量。对于具有对称系数的FIR滤波器，提出的并行结构能够比已有的并行FIR结构节省大量的硬件资源，尤其当滤波器的抽头数较大时效果更明显。具体地，对一个4并行144抽头的FIR滤波器，提出的结构比改进的快速FIR算法(Fast FIR Algorithm, FFA)结构节省36个乘法器(14.3%)，23个加法器(6.6%)和35个延时单元(11.0%)。Abstract: Based on fast convolution algorithm, improved parallel FIR filter structures are proposed for linear- phase FIR filters where the number of taps is a multiple of parallelism. The proposed parallel FIR structures not only use fast convolution algorithm to reduce the number of sub-filters, but also exploit the symmetric coefficients of linear-phase FIR filter to reduce half the number of multiplications in sub-filter section at the expense of additional adders in pre-processing and post-processing blocks. The proposed parallel FIR structures save a large amount of hardware cost for symmetric coefficients from the reported parallel FIR filter structures, especially when the length of the filter is large. Specifically, for a 4-parallel 144-tap filter, the proposed structure saves 36 multipliers (14.3%), 23 adders (6.6%), and 35 delay elements (11.0%) from the improved Fast FIR Algorithm (FFA) structure.
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