一种投票式并行RANSAC算法及其FPGA实现
doi: 10.3724/SP.J.1146.2013.00962
Parallel Voting RANSAC and Its Implementation on FPGA
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摘要: 随机抽样一致(RANdom SAmple Consensus, RANSAC)算法在数据量大,局外点比例高,模型复杂等情况下运算速度明显下降。该文提出一种投票式并行RANSAC算法,在把假设阶段并行化,同时生成多个模型的基础上,提出多个模型并行对同一个数据点投票,直接判断其是否属于局内点的方法,省去了传统方法中根据最佳模型重新筛选数据点的步骤。在以FPGA为代表的并行平台上,该算法可以充分利用其硬件资源和并行处理特性,实现深度流水线的并行运算。实验结果表明该算法不仅拥有更好的鲁棒性,其性能和数据吞吐量还获得了大幅提升。
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关键词:
- FPGA /
- 随机抽样一致(RANSAC) /
- 并行计算
Abstract: RANdom SAmple Consensus (RANSAC) performs poor with the mass of data, high outliers ratio and complicated models. In this paper, a highly parallel voting version of RANSAC is presented. On the basis of parallelizing the hypothetical stage and generating multiple models simultaneously, a novel strategy of voting to determine whether a point belongs to inliers is proposed. Conventional search for the inliers relative to the best model is saved. On parallel platforms represented by FPGA, this algorithm can take advantage of the parallel architecture and characteristics to achieve deep-pipelined parallel computing. Experiments demonstrate the good robustness of the proposed algorithm and its considerable improvement of both speed and throughput.-
Key words:
- FPGA /
- RANdom SAmple Consensus (RANSAC) /
- Parallel computing
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