In the Triple Module Redundancy (TMR) design for the FPGA, the feedback loop of the register will lead to the persistent errors which would have a negative impact on the fault-tolerant capability of the triple module redundancy design, hence the voter insertion in the feedback loop is necessary. This paper presents a triple module redundancy design method to the mapped netlist for the first time, and proposes a voter insertion algorithm based on the critical path. This algorithm proposed can avoid inserting the voter in the critical path and alleviate the negative impact on timing performance during voter insertion. Compared with the similar algorithms, the proposed algorithm can reduce the critical-path delay by 3% to 10% and improve the run time averagely by 35.4% while keeping the design reliability non-decreasing with less than 1% area penalty.