Abstract: An implementing scheme of sum-product algorithm is proposed based on 2-dimation broken line approach, which avoids the look-up table with size related to the exponential of the number of quantization bits and reduces the memory consumption of the decoder. Then, an algorithm called second-minimum value corrected min-sum algorithm is proposed based on the implementing scheme proposed above. The algorithm use three 2-dimension piecewise approach to correct the min-sum algorithm and its performance is very close to that of the floating point sum-product algorithm. The correction process of this algorithm just includes simple arithmetic and logic operations, which is easy to be implemented by FPGA.