兼容多标准的高效运动补偿新结构
doi: 10.3724/SP.J.1146.2010.01134
Hardware-efficient Motion Compensation Architecture for Multi-standard Video Decoder
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摘要: 为有效解决运动补偿的多标准兼容问题，该文提出了一种改进的适用于多标准运动补偿的新插值算法结构，新插值算法基于文中提出的RL(Rounding Last)策略和DTS(Diagonal Two Step)策略，其采用一种统一的两步插值结构有效地兼容了各标准中亮度分量和色度分量的插值。基于新算法，设计实现了一种可重构的多标准运动补偿硬件电路，该电路采用了基于可变块大小的运动补偿结构。实现结果表明，与JM8.4中基于44固定块大小的运动补偿结构相比，所设计的电路使得带宽需求降低了27%~50%，平均单次访问外部存储器的突发长度提高了1.22~2.25倍；电路在125 MHz工作频率下可满足全高清1080 p (19201080) 30帧/s的实时解码需求。Abstract: To solve the problem of Motion Compensation (MC) for multiple standards efficiently, a modified hardware-efficient computing architecture of MC interpolation for multiple standards is developed with the proposed Rounding Last (RL) and Diagonal Two Step (DTS) strategies. A re-configurable MC interpolation hardware based on the new computing architecture is implemented efficiently based on the variable block size. Compared with the fixed-size 44 block-based MC in JM8.4, the bandwidth reduction is about 27%~50%, and the average burst length of each access to the external memory is improved to 1.22~2.25 times longer. When work at 125 MHz, the MC hardware is capable to accomplish the real-time decoding of video streams of the supported standards at 1080 p (19201080) 30 f/s.
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