A Low Power Adaptive Spatio-temporal Bus Coding for Crosstalk Avoidance
-
摘要: 深亚微米片上总线的功耗、布线面积约束和线间串扰是限制总线数据吞吐率的关键因素，为此该文提出一种自适应时空编码方法以降低总线的串扰延迟和功耗。该方法首先采用空间编码将总线分割为两个子总线，从而减小了恶性串扰发生几率；然后通过恶性串扰判决器分别判断子总线的原码数据及反码数据是否存在恶性串扰：对于任意子总线的原码数据与反码数据均存在恶性串扰的情况，传送屏蔽字；否则，选取无恶性串扰且动态功耗小的总线数据形式并传送。采用SPEC标准数据源对算法进行了评估，该方法在消除恶性串扰的同时使总线数据吞吐率提高了62.59%~81.62%，功耗比同类方法降低14.63%~54.67%，对于32位数据总线，仅需7根冗余线，在动态功耗、布线资源和性能方面获得了有效的优化。Abstract: The power consumption, wiring overhead and crosstalk in deep sub-micron on-chip buses are the main facts restricting the bus throughput. An adaptive spatio-temporal bus coding scheme is proposed to reduce crosstalk induced delay and power consumption in the buses. Firstly, on-chip bus is partitioned into two sub-buses by spatio coding to reduce the Worst-Case-Crosstalk (WCC). Then, decisions are made respectively in the two sub-buses whether the original code and inverted code should incur WCC through an arbiter CCA (Crosstalk Class Arbiter). In the case of both original and inverted codes in any sub-bus incurring WCC, a shielding pattern is transmitted; otherwise the WCC-free and energy saving code is transmitted. The proposed scheme is evaluated using the SPEC benchmarks. The results show that the proposed scheme improves the throughput by 62.59% to 81.62% over the un-coded approach and reduces the power consumption by 14.63% to 54.67% compared to the other similar schemes while eliminating the WCC with only 7 wires overhead for a 32 bit bus. The scheme achieves a good enhancement in dynamic power, wiring overhead, and performance.
-
Key words:
- Bus coding /
- Spatio-temporal coding /
- Crosstalk delay /
- ThroughPut (TP) /
- Low power
-
Halak B and Yakovlev A. Throughput optimization for area-constrained links with crosstalk avoidance methods[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2010, 18(6):1016-1019[2]Singh H, Rao R, and Agarwal K, et al..Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2010, 18(1):166-170[6]Duan C, Cordero C V, and Khatri S P. Efficient on-chip crosstalk avoidance CODEC design[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2009, 17(4):551-560[14]Sotiriadis P P and Chandrakasan A P. Bus energy reduction by transition pattern coding using a detailed deep submicrometer bus model[J].IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications.2003, 50(10):1280-1295 -
计量
- 文章访问数: 2847
- HTML全文浏览量: 103
- PDF下载量: 746
- 被引次数: 0
下载:
