Abstract: In RISC-DSP processor, the instructions with dynamic execution cycles cause difficulty to data dependence detection. Based on distributed dependence detection model, the detection operation is expressed by the calculation of the dependence relationship set. The relationship set at next cycle for each pipeline state are calculated. In the mean time, current pipeline state is detected based on the current instruction distribution and signals from each function module. Thus the instruction dependence can be determined one cycle in advance. Logic optimization based on its set operation is also proposed and implemented in our designed processor MediaDSP64. Synthesis result shows that with slight increase in hardware resource and power consumption, the detection operation can be hidden from the original pipeline critical path, and its timing delay can be decreased by about 30%.