Benini L and De Micheli G. Networks on chips: A new SoCparadigm [J]. Computer, 2002, 35(1): 70-78.[2]Murali S, Meloni P, and Angiolini F, et al.. Designingapplication-specific networks on chips with floorplaninformation [C]. ICCAD '06. IEEE/ACM InternationalConference on Computer-Aided Design, San Jose, CA, USA,Nov. 2006: 355-362.[3]Jeang Yuan-Long, Hung Chung-Wei, and ChiangChuen-Muh. A methodology based on maximal-profitspanning tree for designing application specific networks onchip [C][J].ICICIC '06. First International Conference onInnovative Computing, Information and Control, Beijing,Aug.2006, 2:18-21[4]Andreas H, Maarten W, and Arno M, et al.. Applyingdataflow analysis to dimension buffers for guaranteedperformance in networks on chip [C]. NoCS 2008. SecondACM/IEEE International Symposium on Networks-on-Chip,Newcastle University, UK, 7-10 April 2008: 211-212.[5]Hu J and Marculescu R. DyADsmart routing for networkson-chip [C]. Proc. DAC, San Diego, Jun 2004: 260-263.[6]Saastamoinen I and Alho J N M. Buffer implementation forproteo networks-on-chip [C]. Proc Int Symp Circuits andSyst, 2003: 113-116.[7]Dally W J and Towles B. Route packets, not wires: On-chipinterconnection networks [C]. Proceedings of DAC, LasVegas, Nevada, USA, June 18-22, 2001: 683-689.[8]Guerrier P and Greiner A. A generic architecture for on chippacket-switched interconnections [C]. Proceedings ofDATE,Paris, France, March 27-30, 2000: 250-256.[9]Wu Ning, Ge Fen, and Wang Qi. Simulation andperformance analysis of network on chip architectures usingOPNET [C]. ASICON '07. 7th International Conference onASIC, Guilin, China, 22-25 Oct 2007: 1285-1288.[10]Adve V S and Vernon M K. Performance analysis of meshinterconnection networks with deterministic routing [J].IEEE Trans. on Parallel Distrib. Syst.1994, 5(3):225-246[11]Dally W J. Performance analysis of k-ary n-cubeinterconnection networks [J]. Computer, 1990, 39(6):775-785.[12]Kermani P and Kleinrock L. Virtual cut-through: A newcomputer communication switching technique [J]. ComputerNetworks, 1979, 3: 267-289.[13]Kleinrock L. Queueing Systems [M]. Vol.I: Theroy. WileyInterscience, New York, 1975: 17-85.[14]Hu Jingcao, Ogras U Y, and Marculescu R. Applicationspecificbuffer space allocation for networks-on-chip routerdesign [J].IEEE Trans. on Computer-Aided Design ofIntegrated Circuits and Systems.2006, 25(12):2919-2933
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