分组密码处理器的可重构分簇式架构

孟涛; 戴紫彬

doi:10.3724/SP.J.1146.2007.01586

分组密码处理器的可重构分簇式架构

doi: 10.3724/SP.J.1146.2007.01586

孟涛,
戴紫彬

基金项目:

公安部金盾工程(J1GAB23W013)资助课题

计量
- 文章访问数: 3265
- HTML全文浏览量: 134
- PDF下载量: 935
- 被引次数: 0
出版历程
- 收稿日期: 2007-09-29
- 修回日期: 2008-04-07
- 刊出日期: 2009-02-19

Reconfigurable Clustered Architecture of Block Cipher Processor

摘要

摘要: 该文在研究分组密码算法处理特征的基础上，提出了可重构分簇式分组密码处理器架构。在指令的控制下，数据通路可动态地重构为4个32bit簇，2个64bit簇和一个128bit簇，满足了分组密码算法数据处理所需的灵活性。基于分簇结构，提出了由指令显性地分隔电路结构的低功耗优化技术，采用此技术使得整体功耗降低了36.1%。设计并实现了5级流水线以及运算单元内流水结构，处理AES/DES/IDEA算法的速度分别达到了689.6Mbit/s, 400Mbit/s和416.7Mbit/s。
- 分组密码算法;分簇式架构;可重构计算;低功耗设计;流水线
Abstract: This paper presents the reconfigurable clustered architecture of block cipher processor. Appointed by instructions, the data-path of this architecture can be dynamically configured to be three modes, which includes 4clusters, 2clusters and single cluster mode. In different mode, different operations can be done, which improves the flexibility of this processor. Basing on clustered architecture, Explicit-decomposition low-power-design method is presented, which can reduce the power by 36.1%. With 5stages pipeline and wave-pipeline, this processor can work in a high rate. And the performances of AES/DES/IDEA reach 689.6Mbit/s, 400Mbit/s, 416.7Mbit/s.

HTML全文

参考文献(1)

Abnous A and Bagherzadeh N. Pipelining and bypassing in aVLIW Processor [J].IEEE Trans. on Parallel and DistributedSystems.1994, 5(6):658-664[2]Kessler R E. The alpha 21264 microprocessor [J].IEEE Micro.1999, 19(2):24-36[3]Ebeling C, Cronquist D C, and Franklin P. RAPIDReconfigurablePipelined Datapath[C]. The 6th InternationalWorkshop on Field Programmable Logic and Applications,Darmstadt, Germany, Sep. 23-25, 1996: 126-135.[4]Goldstein S C, Schmit H, and Budiu M, et al.. PipeRench: Areconfigurable architecture and compiler [J]. Computer, 2000,33(4): 70-77.[5]Tseng J H and Asanovic K. A speculative control scheme foran energy-efficient banked register file [J].IEEE Trans. onComputers.2005, 54(6):741-751[6]Seznec A, Toullec E, and Rochecouste O. Register writespecialization register read specialization: A path tocomplexity-effective wide-issue superscalar processors [C].The 35th Annual IEEE/ACM International Symposium onMicroarchitecture, Istanbul, Turkey, Nov. 18-22, 2002:383-394.[7]杨晓辉. 面向分组密码处理的可重构设计技术研究[D]. [硕士论文], 解放军信息工程大学, 2007.[8]向楠. 比特置换网络及其在密码处理器中的应用研究[D]. [硕士论文], 解放军信息工程大学, 2007.[9]Yu Xue-rong. Design and implementation of reconfigurableshift unit using FPGAs [C]. The 1st InternationalSymposium on Pervasive Computing and ApplicationsProceedings. Urumchi, Xingjiang, China, August. 3-5, 2006:543-545.[10]Lee Ming Hung, Hwang TingTing, and Huang Shi-yu.Decomposition of extended finite state machine for low powerdesign [C]. The Design, Automation and Test in EuropeConference and Exhibition, Messe Munich, Mar.3-7, 2003:1152-1153.[11]Kuo Wu-An, Hwang TingTing, and Wu A C-H.Decomposition of instruction decoder for low power design[C]. The Design, Automation and Test in Europe Conferenceand Exhibition, CNIT La Defese, Pairs, France, Feb.16-20,2004, Vol.1: 664-665.[12]Hu Chi-Wei and Hwang TingTing. Output-pattern directeddecomposition for low power design [C]. The Design,Automation and Test in Europe Conference and Exhibition,CNIT La Defese, Pairs, France, Feb.16-20, 2004, vol.5:137-140.[13]Elbirt A J. Reconfigurable computing for symmetric-keyalgorithms [D]. [Doctor thesis], Massachusetts: Electrical andComputer Engineering Department University ofMassachusetts Lowell, 2002.曲英杰. 可重组密码逻辑的设计原理[D]. [博士论文], 北京科技大学, 2002.[14]Wu Lisa, Weaver C, and Austin T. CryptoManiac: A fastflexible architecture for secure communication [C]. The 28thAnnual International Symposium on Computer Architecture,Goteborg, Sweden, Jun.30-July4, 2001: l10-119.[15]Buchty R. CRYPTONITE: A programmable cryptoprocessor architecture for high- bandwidth applications [D].[Ph.D.dissertation], Munchen: Institut fur Informatik derTechnischen Universitat Munchen. 2002.

施引文献

资源附件(0)

访问统计