一种高效变速率解调算法

赖卫东; 詹亚锋; 陆建华

doi:10.3724/SP.J.1146.2007.01372

一种高效变速率解调算法

doi: 10.3724/SP.J.1146.2007.01372

基金项目:

国家自然科学基金(60532070)资助课题

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出版历程
- 收稿日期: 2007-08-28
- 修回日期: 2008-04-07
- 刊出日期: 2009-02-19

An Efficient Algorithm for Variable Rate Demodulation

摘要

摘要: 航天器上器件硬件资源和能量受限，对在测控系统中实现变速率解调所需的硬件资源提出了更高的要求。本文提出伪高倍速率解调和重复译码算法，在不降低采样率的情况下可实现不同符号率信号的解调。理论推导证明该方法可达到理想的解调误码性能，且耗费的硬件资源不到经典的DDC(Direct Digital Converter)芯片硬件资源的一半。计算机仿真和实际测试表明该方法能有效应用于微波统一测控系统的变速率解调。
- 变速率解调;重复译码;软译码;抽取
Abstract: In spacecraft, hardware resources and energy are limited, which restricts the hardware consumption of the variable rate demodulation in Telemetry and Telecommand(TTC) systems. This paper proposes an algorithm which accomplishes variable rate demodulation based on pseudo high datarate demodulation and repeated decoding without reducing the sampling rate. It turns out that the performance of the method is equivalent to the ideal result of variable rate demodulation, and the hardware consumption is less than half of that of the classical Direct Digital Converter (DDC) chips. Computer simulations and practical experiments show that the proposed method is effective for variable rate demodulation in TTC systems.

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宗孔德. 多抽样率信号处理[M]. 北京: 清华大学出版社, 1996:1-15, 131-149.Zong Kong-de. Multirate Signal Processing[M]. Beijing: ThePress of Tsinghua University, 1996: 1-15, 131-149.[2]Richard G L. 朱光明等译. 数字信号处理[M]. 第2 版, 北京:机械工业出版社, 2006: 259-269.Richard G L. Digital Signal Processing[M]. 2nd edition.Beijng: China machine press, 2006: 259-269.[3]李菊, 陈禾, 何佩琨, 吴嗣亮. 分数倍抽样率转换器的时变网络结构及其FPGA 实现[J]. 数据采集与处理, 2005, 20(3):24-27.Li Ju, Chen He, He Pei-kun, and Wu Si-lian. Time-varyingnetwork architecture of fractional multiple sampling rateconverter and its FPGA implementation [J]. Journal of DataAcquisition Processing, 2005, 20(3): 24-27.[4]Babic D and Renfors M. Power efficient structure forconversion between arbitrary sampling rates [J].IEEE SignalProcessing Letters.2005, 12(1):1-4[5]张公礼. 全数字接收机理论与技术[M]. 北京: 科学出版社,2005: 86-106.Zhang Gong-li. The Principal and Technology of All-DigitalReceiver [M]. Beijing: The Science Press, 2005: 86-106.[6]Wang Yan, Serpedin E, and Ciblat P. An alternative blindfeedforward symbol timing estimator using two samples persymbol[J].IEEE Trans. on Communications.2003, 51(9):1451-1455[7][7] CCSDS 401.0-B. Radio Frequency and Modulation Systems-Part 1: Earth Stations and Spacecraft. Blue Book [S]. May1999.[8]王新梅, 肖国镇. 纠错码-原理与方法[M]. 修订版, 西安: 西安电子科技大学出版社, 2001: 10-12.Wang Xin-mei and Xiao Guo-zhen. The Error CorrectionCode-Principal and Method[M]. Xian: The Press of XidianUniversity, 2001: 10-12.[9]曹志刚, 钱亚生. 现代通信原理[M]. 北京: 清华大学出版社,1992: 271-276.Cao Zhi-gang and Qian Ya-sheng. The Principal of ModernCommunications[M]. Beijing: The Press of TsinghuaUniversity. 1992: 271-276.[10]Xilinx, Inc. Virtex-4 Datasheets: Virtex-4 Family Overview,Ver2.0.2007:1.[11]陈勇. 基于FPGA 实现高速专用数字下变频器[D]. [硕士论文],电子科技大学, 2005.Chen Yong. High speed dedicated DDC based on FPGA [D].[Master Dissertation], University of Electronic Science andTechnology of China, 2005.[12]Vaidyanathan P P. Multirate digital filters, filter banks,polyphase networks, and applications: A tutorial [C][J].Proc.IEEE.1990, 78(1):56-93[13]Vaidyanathan P P. Filter banks in digital communications [J].IEEE Circuits and Systems Magazine, 2001, 1(2): 4-25.[14]Intersil Corporation. HSP50214B Datasheet, FN4450(4).2007: 1-2.[15]Analog Devices, Inc. AD6620 Datasheet, Rev A. 2001: 1-3.[16]Texas Instruments Incorporated. GC4016 Datasheet, Rev1.0.2001: 1-2.

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