互连线串扰耦合噪声的ABCD矩阵模型
doi: 10.3724/SP.J.1146.2007.01156
ABCD Modeling of Crosstalk Coupling Noise of Interconnects
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摘要: 高频互连线间的相互耦合和相互感应是产生串扰的一个重要因素。已有文献利用二端口网络ABCD矩阵从理论上求出了耦合互连线阶跃响应，但该方法对互感描述不准确，导致计算复杂，且对串扰耦合噪声的估计不够准确。该文根据互感的基本定义，修改了原模型中互感的表示方法，提出了一个新的ABCD矩阵级联模型，对LTCC工艺互连线的串扰耦合噪声进行分析，并将得到的ABCD模型分析结果与ADS软件的仿真结果对比，验证了改进的ABCD模型的准确性。
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关键词:
- ABCD矩阵;串扰;Pad近似
Abstract: Coupling capacitance and mutual inductance are important factors of crosstalk losses in high frequency. ABCD models with improper mutual inductance description have been reported to be used to obtain step response of coupling interconnects . In this paper, a more accurate ABCD model with modified mutual inductance is introduced. Finally, crosstalk coupling noise of interconnects in LTCC technology is analyzed using ADS simulation to verify the improved ABCD model. -
Palit Ajoy K and Anheier Walter. Reduced order longinterconnect modeling. Proc. of 15th GI/GMM/ITGWorkshop on Testmethoden und ZuverLassigkeit vonSchaltungen und Systemen, 23-25, Timmendorfer Strand,Germany, 23.03.2003 . 25.03 2003: 42-47.[2]Palit Ajoy K and Anheier Walter. Estimation of signalintegrity loss through reduced order interconnect model. Proc.IEEE-SPI, Siena, Italy, 2003: 163-166.[3]Palit Ajoy K and Anheier Walter. Test pattern generationbased on predicted signal integrity loss through reduced orderinterconnect model. 16-ITG-GI-GMM-Workshop Testmethodenund Zuverl Sigkeit von Schaltungen und Systemen,Dresden, Germany, 29.02.2004-02.03.2004: 84-88.[4]Palit Ajoy K, Anheier Walter, and Meyer V. Modeling andanalysis of crosstalk coupling effect on the victiminterconnect using the ABCD network model. 19th IEEEInternational Symposium on Defect and Fault Tolerance inVLSI Systems, Cannes, France, 10-13. Oct. 2004: 174-182.[5]Palit Ajoy K, Anheier Walter, and Schloeffel J. A new,flexible and very accurate crosstalk fault model to analyze theeffects of coupling noise between the interconnects on signalintegrity losses in deep submicron chips. Proceedings of 14thIEEE-Asian Test Symposium, Calcutta, India, 18.12.2005 .21.12. 2005: 22-27.[6]Bogatin Eric 挊, 棝嬍嶳.. 怣崋姰惍惈暘愅. .巕岺.弌斉幮, 2006.1: 124-128.[7]Banerjee K and Mehrotra A. Analysis of on-chip inductanceeffects for distributed RLC interconnects[J].IEEE Trans. onCAD of Integrated Circuits and Systems.2002, 21(8):904-915 -
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