FPGA通用开关盒层次化建模与优化
doi: 10.3724/SP.J.1146.2007.00787
Hierarchical Modeling and Optimization of Versatile FPGA SB
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摘要: 国际上权威的通用布局布线工具（Versatile Place and Route tool，VPR）所支持的开关盒（Switch Box，SB）结构限定在Disjoint，Wilton和Universal3种类型，并且通道内同种类型的互连线必须相邻排列。针对这两个约束，该文提出了FPGA（Field Programmable Gate Array）层次化通用开关盒模型，可涵盖FPGA中的任意开关盒结构，并基于这种模型，提出了具有更高布通率的新型开关盒结构JSB（Joint Switch Box，JSB），与Disjoint，Wilton和Universal结构相比，布通率分别提高了10.1%，3.3%和4.6%；还通过优化分布FPGA中互连线，大幅度减小了电路延时，在相同工艺参数和相同开关盒的条件下，比VPR的布线时延关键路径平均缩短了10.4%。Abstract: There are two restrictions in the Versatile Place and Route tool, VPR. It can only support three kinds of switch box architecture, which are Disjoint, Wilton and Universal, and the same type of wires in a channel must be distributed next to each other. To break through these two restrictions, this paper proposes a hierarchical versatile switch box model, covering arbitrary switch box architecture in FPGA. Based on this model, this paper designs new switch box architecture, JSB. Comparing with Disjoint, Wilton and Universal architecture, JSB improves greatly routability by 10.1%, 3.3% and 4.6% respectively. Furthermore, in this paper, optimizing the distribution of wires reduces the timing of critical path by 10.4% on average, compared with VPR.
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