一种低译码复杂度的Turbo架构LDPC码
doi: 10.3724/SP.J.1146.2006.00824
A Low Decoding Complexity Gallager Code with Turbo Architecture
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摘要: 针对低密度奇偶校验(LDPC)码较大的译码复杂度和RAM占用，该文提出了一种低译码复杂度的Turbo架构LDPC码并行交织级联Gallager码 (Parallel Interleaved Concatenated Gallager Code，PICGC)。该文给出了PICGC的设计方法和编译码算法，并分析比较了PICGC译码器与LDPC译码器所需的RAM存储量，推导出RAM节省比的上界。理论分析和仿真结果表明，PICGC以纠错性能略微降低为代价，有效地降低译码复杂度和RAM存储量，且译码时延并未增加，是一种有效且易于实现的信道编码方案。
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关键词:
- LDPC码;级联码;译码复杂度
Abstract: Be aimed at lower complexity and RAM requirement of Low Density Parity Check (LDPC) decoder, a new class of concatenated codes called Parallel Interleaved Concatenated Gallager Code (PICGC), based on Turbo architecture and LDPC codes, is presented. In this paper, design, encoding and decoding algorithms of PICGC are studied. The RAM requirement for PICGC decoder is analyzed and compared to LDPC decoder, and an upper bound of memory-saving ratio is derived. The theoretical analysis and simulation results demonstrate that PICGC can reduce decoding complexity and RAM requirement significantly and maintain decoding delay with little sacrifice in performance in comparison to conventional LDPC codes. PICGC is an effective and feasible channel coding scheme. -
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