快速建立时间的自适应锁相环
doi: 10.3724/SP.J.1146.2005.01548
An Adaptive PLL Architecture to Achieve Fast Settling Time
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摘要: 该文简要讨论了环路性能(建立时间，相位噪声和杂散信号)和环路参数(带宽，相位裕度等)的相互关系。提出并分析了一种自适应的具有快速建立时间的锁相环结构及其关键模块(鉴相鉴频器和电荷泵)。该结构基于两个环路：粗调谐环路和精调谐环路。粗调谐环路用于快速收敛，而精调谐环路用于精细的调整。环路参数调整连续发生，无需切换环路滤波器元件和外面的控制信号。基于SMIC 0.18m 1.8V CMOS工艺的Spectre仿真表明：粗调谐鉴相鉴频器能够有效地关断粗调谐回路；电荷泵上下电流具有小于0.1%的静态失配特性；在相同的环路带宽下与传统的锁相环相比，自适应锁相环能减少超过30%的建立时间。
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关键词:
- 锁相环;鉴相鉴频器;电荷泵
Abstract: The relationships between loop performance (settling time, phase noise and spur signal) and loop parameters (bandwidth and phase margin) are briefly discussed in the paper. An adaptive Phase-Locked Loop (PLL) with a fast settling time and its key blocks including Phase-Frequency Detector (PFD) and charge pump are then proposed and analyzed. The proposed architecture is based on two tuning loops: a coarse-tuning loop and a fine-tuning loop. The coarse-tuning loop is used for fast convergence and the fine-tuning loop is used to complete fine adjustments. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside control signal. Spectre simulation based on SMIC 0.18m 1.8V supply voltage CMOS technology shows that coarse-tuning PFD can effectively cut off coarse-tuning loop, and the charge pump has a 0.1% up/down current mismatching characteristic. The adaptive PLL can reduce settling time over 30% in comparison to the conventional PLL in the same loop bandwidth. -
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