Viterbi译码器回溯算法实现研究
doi: 10.3724/SP.J.1146.2005.00614
Study on Implementation of Traceback Algorithm in Viterbi Decoders
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摘要: 该文介绍了两种Viterbi译码器回溯译码算法，通过对这两种算法硬件实现结构上的优化，给出了这两种算法的FPGA实现方法，比较了两种实现方法的优缺点。最后将其应用在实际的Viterbi译码器设计上，验证了算法实现的正确性。
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关键词:
- Viterbi译码;回溯算法;FPGA
Abstract: This paper discusses two traceback algorithms for Viterbi decoder. The realization methods for the traceback algorithms with FPGA are given through optimization for the hardware architecture. The comparison between the two realization methods is given. Finally, the two realization methods are applied to Viterbi decoder, and both simulation and hardware test show that the presented implementation methods are correct. -
[1] Viterbi A J. Error bounds for convolutional codes and an asymptotically optimum decoding algorithm [J].IEEE Trans. on Information Theory.1967, 13(2):260-269 [2] Rader C M. Memory management in a Vitrbi decoder [J].IEEE Trans. on Communications.1981, 29(9):1399-1401 [3] Feygin G and Gulak P G. Architectural tradeoffs for survivor sequence memory management in Viterbi decoders [J].IEEE Trans. on Communications.1993, 41(3):425-429 [4] Black P J and Meng T H. A 140-Mb/s, 32-state, radix-4 Viterbi decoder [J].IEEE Journal of Solid-State Circuits.1992, 27(12):1877-1885 [5] Corporation A. Cyclone Device Handbook, Volume 1 [M]. 2003. -
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