硅基紧凑型偏振分束旋转器的逆向设计

惠战强; 张兴龙; 韩冬冬; 李田甜; 巩稼民

doi:10.11999/JEIT250858

硅基紧凑型偏振分束旋转器的逆向设计

doi: 10.11999/JEIT250858 cstr: 32379.14.JEIT250858

惠战强^{1, 2, ,},
张兴龙^{1, 2},
韩冬冬^{1, 2},
李田甜^{1, 2},
巩稼民^{1, 2}

1.
西安邮电大学电子工程学院西安 710121
2.
陕西省微波光子与下一代宽带通信技术国际科技合作基地西安 710121

基金项目: 国家重点研发计划项目(2022YFB2903201)，陕西省创新能力支撑计划项目(2022PT15)

详细信息

作者简介:
惠战强：男，教授，研究方向为光纤通信技术、全光信号处理、集成光电子器件与光芯片

张兴龙：男，硕士生，研究方向为集成光子器件和光纤通信仿真设计

通讯作者:
惠战强　zhanqianghui@xupt.edu.cn

中图分类号: TN29
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- 文章访问数: 53
- HTML全文浏览量: 14
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- 被引次数: 0
出版历程
- 修回日期: 2025-11-13
- 录用日期: 2025-11-13
- 网络出版日期: 2025-11-18

Inverse Design of a Silicon-Based Compact Polarization Splitter-Rotator

HUI Zhanqiang^{1, 2
, ,},
ZHANG Xinglong^{1, 2},
HAN dongdong^{1, 2},
LI Tiantian^{1, 2},
GONG Jiamin^{1, 2}

1.
The School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China
2.
The Shaanxi Province International Science and Technology Cooperation Base for Microwave Photon and Next Generation Broadband Communication Technology, Xi’an 710121, China

Funds: National Key Research and Development Program Project (2022YFB2903201), Shaanxi Provincial Innovation Capacity Support Program Project (2022PT15)

摘要

摘要: 片上偏振分束旋转器(Polarization Splitter-Rotator, PSR)作为调控光波偏振态的核心集成光子器件之一，其微型化设计是实现高密度光子集成电路(Photonic Integrated Circuit, PIC)的关键。本文基于绝缘体上硅平台(Silicon-on-Insulator, SOI)，采用逆向法设计了一种超紧凑偏振分束旋转器，通过将动量优化算法(Momentum-based Optimization)与伴随法(Adjoint Method)相结合，提高了设计效率。并且，进一步通过空气孔融合将孔半径控制在50 nm至250 nm之间，降低了器件的制造难度。数值分析结果表明：该器件在1520-1575 nm波段内实现了低插入损耗(TM₀<1 dB，TE₀<0.68 dB)，低串扰(TM₀<-23 dB，TE₀<–25.2 dB)和高偏振消光比(TM₀>17 dB，TE₀>28.5 dB)。器件尺寸仅为2.5 μm×5 μm。工艺容差分析表明，在蚀刻深度偏移±9 nm，蚀刻半径偏移±5 nm时，在1520-1540nm带宽范围内，性能没有明显劣化，具有良好的制造鲁棒性。
- 偏振分束旋转器 /
- 逆向设计 /
- 伴随法 /
- 动量优化算法 /
- 空气孔融合
Abstract: Objective The integrated polarization splitter-rotator (PSR), as one of the key photonic devices for manipulating the polarization state of light waves, has been widely used in various photonic integrated circuits (PICs). For PICs, device size becomes a major bottleneck limiting integration density. Compared to traditional design methods, which suffer from being time-consuming and producing larger device sizes, inverse design optimizes the best structural parameters of integrated photonic devices according to target performance parameters by employing specific optimization algorithms. This approach can significantly reduce device size while ensuring performance and is currently used to design various integrated photonic devices, such as wavelength/mode division multiplexers, all-optical logic gates, power splitters, etc. In this paper, the Momentum Optimization algorithm and the Adjoint Method are combined to inverse design a compact PSR. This can not only significantly improve the integration level of PICs but also offers a design approach for the miniaturization of other photonic devices. Methods First, based on a silicon-on-insulator (SOI) wafer with a thickness of 220 nm, the design region was discretized into 25×50 cylindrical elemental structures. Each structure has a radius of 50 nm and a height of 150 nm and is filled with an intermediate material possessing a relative permittivity of 6.55. Next, the adjoint method was employed for simulation to obtain gradient information over the design region. This gradient information was processed using the Momentum Optimization algorithm. Based on the processed gradient, the relative permittivity of each elemental structure was modified. During the optimization process, the momentum factor in the Momentum Optimization algorithm was dynamically adjusted according to the iteration number to accelerate the optimization. Meanwhile, a linear bias was introduced to artificially control the optimization direction of the relative permittivity. This bias gradually steered the permittivity values towards those of silicon and air as the iterations progressed. Upon completion of the optimization, the elemental structures were binarized based on their final relative permittivity values: structures with permittivity less than 6.55 were filled with air, while those greater than 6.55 were filled with silicon. At this stage, the design region consisted of multiple irregularly distributed air holes. To compensate for the performance loss incurred during binarization, the etching depth of air holes (whose pre-binarization permittivity was between 3 and 6.55) was optimized. Furthermore, adjacent air holes are merged to reduce manufacturing errors. This resulted in a final device structure composed of air holes with five distinct radii. Among these, three types of larger-radius air holes were selected. Their etching radii and depths were further optimized to compensate for the remaining performance loss. Finally, the device performance was evaluated through numerical analysis. Key parameters calculated include insertion loss (IL), crosstalk (CT), polarization extinction ratio (PER), and bandwidth. Additionally, tolerance analysis was performed to assess the robustness of the performance. Results and Discussions This paper presents the design of a compact PSR based on a 220-nm-thick SOI wafer, with dimensions of 5 µm in length and 2.5 µm in width. During the design process, the momentum factor within the Momentum Optimization algorithm was dynamically adjusted: a large momentum factor was selected in the initial optimization stages to leverage high momentum for accelerating escape from local maxima or plateau regions, while a smaller momentum factor was used in later stages to increase the weight of the current gradient. Compared to other optimization methods, the algorithm employed in this work required only 20%-33% of the iteration counts needed by other algorithms to achieve a Figure of Merit (FOM) value of 1.7, significantly enhancing optimization efficiency. Numerical analysis results demonstrate that this device achieves the following performance across the 1520-1575 nm wavelength band: low IL (TM₀<1 dB,TE₀<0.68 dB), low CT: (TM₀<-23 dB, TE₀<-25.2 dB), high PER: (TM₀>17 dB, TE₀>28.5 dB), process tolerance analysis indicates that the device exhibits robust fabrication tolerance. Within the 1520-1540 nm bandwidth, performance shows no significant degradation under variations of etching depth offset ±9 nm, etching radius offset ±5 nm. This demonstrates its excellent manufacturability robustness. Conclusions Through numerical analysis and comparison with devices designed in other literature, this work clearly demonstrates the feasibility of combining the adjoint method with the Momentum Optimization algorithm for designing the integrated PSR. Its design principle involves manipulating light propagation to achieve the polarization splitting and rotation effect by adjusting the relative permittivity to control the positions of the air holes. Compared to traditional design methods, inverse design enables the efficient utilization of the design region, thereby achieving a more compact structure. The PSR proposed in this work is not only significantly smaller in size but also exhibits larger fabrication tolerance. It holds significant potential for application in future large-scale PICs chips, while also offering valuable design insights for the miniaturization of other photonic devices.
- polarization splitter-rotator /
- inverse design /
- adjoint method /
- momentum optimization algorithm /
- air hole merging

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图 1 设计的PSR示意图

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图 2 设计前结构初始状态确定图

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图 3 不同优化算法的性能比较

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图 4 优化流程图

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图 5 相对介电常数介于3-6.55的空气孔优化示意图

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图 6 FOM值随大空气孔蚀刻半径，蚀刻深度的变化图

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图 7 TE₀，TM₀模式传输图以及输入输出端口电场分布图

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图 8 TE₀，TM₀模式分别输入时的性能随波长变化图

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图 9 TE₀，TM₀模式在蚀刻深度±9 nm和蚀刻半径±5 nm公差范围内的性能参数

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表 1 蚀刻深度公差性能表

Mode	Tolerance (nm)	Bandwidth (nm)	IL (dB)	CT (dB)	PER (dB)
TE₀	+9	1520–1575	<0.8	<–25.4	>26.3
	–9	1520–1575	<0.8	<–26	>29.2
TM₀	+9	1520–1575	<1.8	<–22.4	>11
	–9	1520–1575	<2	<–27.1	>15.6

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表 2 蚀刻半径公差性能表

Mode	Tolerance (nm)	Bandwidth (nm)	IL (dB)	CT (dB)	PER (dB)
TE₀	+5	1520–1575	<1	<–23.9	>26
	–5	1520–1575	<0.9	<–28.9	>25.2
TM₀	+5	1520–1575	<2.1	<–27.2	>11.6
	–5	1520–1575	<1.5	<–22.1	>17.2

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表 3 与其它片上PSR的比较

Reference	Length (μm)	IL_TM (dB)	CT_TM (dB)	PER_TM (dB)	Bandwidth (nm)	Band
[12] -Sim	24	<1	—	>15	150	C
[20] -Exp	405	<2	—	>11	160	C
[31] -Sim	7.95	<1	<-26	>15	40	C
[43] -Exp	17	<1	<-20	—	50	O
[44] -Sim	6	<3	<-20	—	73	C
[45] -Sim	120	<0.5	<-50	—	200	C
[46] -Sim	86	<2.8	<-34	—	200	O
[47] -Exp	170	<0.8	<-18	—	60	C
This work	5	<1	<-23	>17	55	C

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