天基计算芯片：现状、趋势与关键技术

魏肖彤; 许浩博; 尹春笛; 黄俊培; 孙文昊; 徐文浚; 王颖; 刘垚圻; 孟范涛; 闵丰; 王梦迪; 韩银和

doi:10.11999/JEIT250633

天基计算芯片：现状、趋势与关键技术

doi: 10.11999/JEIT250633 cstr: 32379.14.JEIT250633

魏肖彤^{1, 2, 3, 4},
许浩博^{1, 2},
尹春笛^{1, 2},
黄俊培^{1, 2},
孙文昊^{1, 2},
徐文浚^{1, 2},
王颖^{1, 2},
刘垚圻^{1, 2},
孟范涛^{1, 2},
闵丰^{1, 2},
王梦迪^{1, 2},
韩银和^{1, 2, ,}

1.
中国科学院计算技术研究所北京 100190
2.
中国科学院计算技术研究所智能计算机研究中心北京 100190
3.
中国科学院大学杭州高等研究院杭州 310024
4.
中国科学院大学北京 101408

基金项目: 国家自然科学基金 (62025404, 62495104)，北京市自然科学基金(L241013)

详细信息

作者简介:
魏肖彤：男，博士生，研究方向为计算机体系结构，芯片架构设计

许浩博：男，副研究员，研究方向为计算机系统结构，专用芯片

尹春笛：男，硕士生，研究方向为计算机体系结构，芯片设计

黄俊培：男，博士生，研究方向为计算机体系结构，芯片架构设计

孙文昊：男，硕士生，研究方向为计算机体系结构

徐文浚：男，硕士生，研究方向为计算机体系结构，大模型推理优化

王颖：男，研究员，研究方向为专用处理器体系结构，集成芯片系统

刘垚圻：男，副研究员，研究方向为天基计算，通感算一体化

孟范涛：男，主任设计师，研究方向为星上电子系统架构研究与星载计算机产品设计

闵丰：男，助理研究员，研究方向为计算机系统结构，专用芯片

王梦迪：女，助理研究员，研究方向为领域专用处理器架构设计、芯粒集成

韩银和：男，研究员，研究方向为计算机体系结构和芯片，智能机器人，智能硬件，数据计算芯片和计算系统

通讯作者:
韩银和　yinhes@ict.ac.cn

中图分类号: TP302.1
计量
- 文章访问数: 38
- HTML全文浏览量: 23
- PDF下载量: 6
- 被引次数: 0
出版历程
- 收稿日期: 2025-07-04
- 修回日期: 2025-09-05
- 网络出版日期: 2025-09-17

Space-based Computing Chips: Current Status, Trends and Key Technique

WEI Xiaotong^{1, 2, 3, 4},
XU Haobo^{1, 2},
YIN Chundi^{1, 2},
HUANG Junpei^{1, 2},
SUN Wenhao^{1, 2},
XU Wenjun^{1, 2},
WANG Ying^{1, 2},
LIU Yaoqi^{1, 2},
MENG Fantao^{1, 2},
MIN Feng^{1, 2},
WANG Mengdi^{1, 2},
HAN Yinhe^{1, 2
, ,}

1.
SKLP, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
2.
Research Center for Intelligent Computing Systems, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
3.
Hangzhou Institute for Advanced Study, Hangzhou 310024, China
4.
University of Chinese Academy of Sciences, Beijing 101408, China

Funds: The National Natural Science Foundation of China (62025404, 62495104), Beijing Natural Science Foundation (L241013)

摘要

摘要: 随着航天技术的快速发展，天基计算芯片作为空间信息系统的核心器件，承担着数据处理、任务控制和通信支持等关键功能，其重要性日益凸显。天基计算芯片不仅决定了空间任务的执行效率和可靠性，还在极端环境下为航天器的长期稳定运行提供保障。该文通过回顾天基计算芯片的发展历程，以探讨其未来发展方向。首先按照结构功能划分，从通用处理器(CPU)、现场可编程门阵列(FPGA)和专用芯片3方面对天基计算芯片的发展现状进行归纳和总结；然后深入分析其与地面芯片的主要区别，探讨针对辐射效应等空间环境挑战的关键容错技术，并从不同层面阐述已有的技术方法；最后论述了天基计算芯片未来的主要发展方向，即大算力、商用现货 (COTS)器件广泛应用、第五代精简指令集(RISC-V)架构。该文能够帮助读者了解该领域现状，掌握关键问题，并为后续的相关研究工作提供有价值的参考和启示。
- 天基计算芯片 /
- 容错技术 /
- 大算力 /
- COTS器件 /
- RISC-V架构
Abstract: Significance With the continuous advancement of aerospace technology and the growing demand for space applications, space-based computing chips have assumed increasingly important strategic roles as core hardware infrastructure of space information systems. As the technological foundation enabling intelligent data processing and reliable communications for spacecraft—including satellite platforms, space stations, and deep space probes—space-based computing chips not only safeguard national security and support economic development but also play an irreplaceable role in serving civilian needs. Although existing survey literature has systematically reviewed the development of aerospace Central Processing Units (CPUs), comprehensive analyses of other key components within the space-based computing chip ecosystem remain limited. To address this gap, this paper systematically examines the technological evolution of various space-based computing chips and their principal fault-tolerant mechanisms, and further explores potential future trends in this field. Progress This paper adopts a functional architecture-oriented classification to systematically analyze and summarize the current technological status of space-based computing chips across three dimensions: CPU, Field-Programmable Gate Array (FPGA), and dedicated chip. For CPU technology, a classification study of general-purpose processors widely used in aerospace applications is conducted based on instruction set architectures, with in-depth analysis of the technical characteristics and representative products of various architectures, together with an objective evaluation of their advantages and limitations in space environments. In the FPGA domain, the technical specifications and performance characteristics of mainstream space-grade FPGA products, both domestic and international, are comprehensively reviewed to provide a reference for application selection. For dedicated chips, a detailed categorization is carried out according to functional architectural features and application scenario requirements, covering Digital Signal Processing (DSP) chips for signal processing acceleration, Graphics Processing Unit (GPU) chips for graphics computation, and Neural Processing Unit (NPU) chips for space-based artificial intelligence applications, thereby systematically clarifying the applicability of different architectures in complex space environments. In addition, this paper presents an in-depth analysis of the key fault-tolerant technology framework for space-based computing chips at multiple levels, including system, architecture, circuit, and process library, and provides a comprehensive evaluation of the technical advantages, application limitations, and development prospects of various fault-tolerant mechanisms. This analysis offers theoretical guidance for the reliability design of space-based computing chips. Conclusions This review systematically summarizes the technological development of space-based computing chips, providing a comprehensive analysis of the architectural characteristics of different chip types and their associated fault-tolerant technology frameworks, while elucidating the applicable scenarios and technical limitations of various fault-tolerant mechanisms. The central principle of fault-tolerant design for space-based computing chips is to achieve effective detection and correction of circuit faults through redundancy mechanisms. This paper offers an in-depth analysis of the implementation principles and application characteristics of fault-tolerant technologies at four hierarchical levels: system, architecture, circuit, and process library. Although these multi-level approaches substantially improve system reliability, they inevitably introduce hardware resource overhead and performance penalties. Therefore, the engineering design of space-based computing chips requires optimized strategies that combine multi-level fault-tolerant technologies according to specific reliability requirements, aiming to balance reliability, cost, and performance to meet the intended design objectives and technical specifications. Prospects Looking ahead, space-based computing chips present broad prospects in high computing capability, widespread adoption of Commercial Off-The-Shelf (COTS) devices, and the development of Reduced Instruction Set Computer – Five (RISC-V) instruction set architectures. With the rapid advancement of space technology, space-based systems are undergoing a transformation from traditional single-function platforms to integrated platforms characterized by multi-task collaboration, autonomy, and intelligence. Real-time data processing, multi-task parallel computing, and intelligent decision-making have become the principal driving forces in the evolution of space-based computing technology, all of which demand robust computational foundations. Compared with traditional radiation-hardened specialized devices, COTS devices are emerging as a major trend in space-based computing chip development due to their advantages in cost-effectiveness, computational performance, shorter development cycles, and product diversity. In addition, RISC-V, as an open-source instruction set architecture, offers unique advantages and significant potential for space-based computing chip innovation through its modular design philosophy, exceptional scalability, and open ecosystem.
- Space-based computing chips /
- Fault-tolerant technology /
- High computing capability /
- Commercial Off-The-Shelf (COTS) /
- RISC-V

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图 1 宇航通用处理器发展路线

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图 2 系统层不同容错架构

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表 1 天基芯片中通用处理器按指令架构分类

指令集架构	处理器芯片	年份	国家/地区	核数/位宽	主频	功耗	工艺节点	抗辐射能力
X86	Intel 80386SX	1988	美国	单核32位	20.0 MHz	1.0 W	1.50 μm	无硬化，需屏蔽防护
X86	AMD Steppe Eagle	2021	瑞典	四核64位	1.0 GHz	5.0–10.0 W	28 nm	CTOS，未加固
SPARC	TSC695E	2001	美国	单核32位	25.0 MHz	1.0 W	0.5 μm	TID～300 krads
	AT697F(LEON2)	2011	法国	单核32位	90.0 MHz	0.5 W	0.18 μm	TID～100 krads, SEU加固
	BM3803	2011	中国	单核32位	8.0-12.0 MHz	< 1.0 W	0.35 μm	TID～50 krads级，TMR加固
	BM3823	2018	中国	单核32位	300.0 MHz	2.0 W	65 nm	TMR加固, SEL≥75 (MeV·cm²)/mg
	GR740(LEON4FT)	2021	美国	四核32位	250.0 MHz	7.0 W	65 nm	TID>100 krads, TMR加固
ARM	Phytium D2000	2020	中国	八核64位	2.3 GHz	25.0 W	14 nm	CTOS，支持ECC校验
ARM	VORAGO VA7230	2021	美国	双核64位	1.5 GHz	< 10.0 W	—	TID≥100 krads, SEL≥60 (MeV·cm²)/mg
RISC-V	NOEL-V	2020	瑞典	64/32位	—	—	—	存储器支持纠正4bits相邻错误
	HPSC (NASA)	2022	美国	十核64位	0.1-1.0 GHz	< 15.0 W	7/14 nm	TID～100 krads, SEL免疫80 MeV
	AS32S601	2024	中国	双核32位	180.0 MHz	135.0～275.0 mW	—	SEU：10⁻⁵次/器件·天
MIPS	Loongson 3A5000	2015	中国	四核64位	2.5 GHz	30.0 W	12 nm	CTOS，部分加固版本研制中

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表 2 国内外太空FPGA产品特性

FPGA型号	制造商	架构/工艺	等效逻辑规模	抗辐射能力	特点及应用
Xilinx Virtex-5QV	AMD (美)	SRAM FPGA /65 nm	130万逻辑门	TID >1 Mrads; SEL≥75 MeV·cm²/mg	首款高性能抗辐射FPGA，用于图像处理
XQRKU060	AMD (美)	SRAM FPGA /20 nm	100万逻辑门	TID >100 krads； SEE加固	支持高速收发器，用于宽带通信载荷
Microchip RTAX2000	Microchip (美)	Anti-fuse FPGA/150 nm	200万逻辑门	TID >1 Mrads	抗熔丝工艺，配置不可重构，适用于长寿命任务控制逻辑
Microchip RTG4	Microchip (美)	Flash FPGA /28 nm	15万逻辑单元	TID >100 krads	闪存工艺，无配置单粒子翻转，中高轨DSP和控制逻辑
BRAVE NG-Medium	NanoXplore (欧)	SRAM FPGA /28 nm	5万 LUT6	TID >100 krads; SEL～ 68 MeV· cm²/mg	用于ESA小卫星接口和控制逻辑
JFM4VSX55RH	复旦微 (中)	SRAM FPGA	1000万逻辑门	TID 200 krads; SEL ～ 81 MeV·cm²/mg	已在高分卫星上验证，用于图像处理

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表 3 架构容错技术对比

技术	描述	优缺点
TCLS	配置3个内核执行同一任务，进行周期级比对	效率最高的纠错率，但最大的面积与功耗开销
HMR	构建锁步控制矩阵，实现TCLS、DCLS与独立模式快速切换	面积、性能与可靠度之间均衡折中
ODGR	在每3个核间配置多数表决模块，通过软件配置启用或释放冗余模块	额外硬件开销最小，依赖软件恢复周期长

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表 4 电路容错技术对比

技术	描述	应用场景
ECC	检测和纠正内存错误	内存、处理器
TMR	3个模块投票，容忍单一故障	航空航天
BIST	自我检测，切换冗余组件	处理器、存储器

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表 5 抗辐照工艺库技术

技术	描述	辐射耐受性
SOI	绝缘基底，减少电荷收集	1000～3000 krad
宽带隙材料	耐受深层缺陷	高(具体数值待定)
DICE锁存器	冗余节点提高抗辐射能力	500 krad+
非易失性磁阻材料	优化隧道结的材料和结构	100 krad，降低写功耗

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表 6 国内外太空项目使用COTS器件用例

项目	COTS器件	功能描述
SpaceX星链	Broadcom BCM2711^[88]处理器	数据处理和任务控制
	NVIDIA Jetson TX2^[89]GPU	加速图像处理与深度学习处理
	COTS NAND Flash、DRAM存储芯片	数据记录与存储，支持冗余设计与纠错机制
	ADI射频前端模块、TI射频控制器	收发射频信号并进行处理
	电源管理芯片功率放大器^[90]	发射功率放大器
NASA CubeSat^[93]	商用 S/UHF/X 波段射频通信模块	实现地面通信、数据下行与实验验证
银河航天低轨宽带通信卫星	ARM架构MCU、Xilinx Kintex-7 抗辐射FPGA	通过TMR设计保障星上逻辑稳定性，并搭配 ARM 架构 MCU 加强控制任务^[91]
长光卫星中遥感卫星	COTS GPU/SoC	实时图像处理与压缩，支持高分辨率遥感任务^[92]

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