STT-MRAM绝对差值原位计算驱动的轻量型AdderNet电路设计

王黎勋; 张跃军; 李琪康; 张会红; 温亮

doi:10.11999/JEIT250627

STT-MRAM绝对差值原位计算驱动的轻量型AdderNet电路设计

doi: 10.11999/JEIT250627 cstr: 32379.14.JEIT250627

1.
宁波大学信息科学与工程学院宁波 315211
2.
中国人民武装警察部队海警学院电子技术系宁波 315801

基金项目: 国家自然科学基金(62474100, 62174121, 62134002)，浙江省“尖兵领雁+X”科技计划项目(2025C01063)，宁波市科创甬江2035重点研发计划(2024Z139)，慈溪市重点研发专项(CZ2025006)，宁波大学研究生科研创新项目

详细信息

作者简介:
王黎勋：男，博士生，研究方向为低功耗存算一体电路设计及实现

张跃军：男，教授，研究方向为低功耗、高信息密度集成电路理论和设计

李琪康：男，博士生，研究方向为高效深度神经网络加速器设计

张会红：女，副教授，研究方向为控制理论与应用、低功耗集成电路理论与优化设计

温亮：男，博士，研究方向为低功耗存储器电路设计及实现

通讯作者:
张跃军　zhangyuejun@nbu.edu.cn

中图分类号: TN403
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出版历程
- 收稿日期: 2025-04-28
- 修回日期: 2025-09-17
- 网络出版日期: 2025-09-19
- 刊出日期: 2025-09-24

Lightweight AdderNet Circuit Enabled by STT-MRAM In-Memory Absolute Difference Computation

1.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
2.
Department of Electronic Technology, China Coast Guard Academy, Ningbo 315801, China

Funds: The National Natural Science Foundation of China (62474100, 62174121, 62134002), “Vanguard Geese Leading and X” Science and Technology Program of Zhejiang Province (2025C01063), The Key R&D Program of Ningbo Science and Technology Yongjiang 2035 (2024Z139), The Key R&D Program of Cixi (CZ2025006), The Graduate Student Scientific Research and Innovation Project of Ningbo University

摘要

摘要: 随着人工智能研究的不断深入，卷积神经网络(Convolutional Neural Networks, CNN)在资源受限环境中的部署需求不断上升。然而，受限于冯·诺依曼架构，CNN加速器随着部署模型深度增加，卷积核逐层堆叠所引发的乘累加运算呈现超线性增长趋势。为此，该文提出一种基于自旋转移矩磁性随机存储器(Spin Transfer Torque-Magnetoresistive Random Access Memory, STT-MRAM)的轻量型加法神经网络(AdderNet)加速电路设计方案。该方案首先将L1范数引入存算一体架构，提出STT-MRAM绝对差值原位计算方法，以轻量级加法取代乘累加运算；其次，设计基于磁阻状态映射的可配置全加器，结合稀疏优化策略，跳过零值参与的冗余逻辑判断；最后，进一步构建支持单周期进位链更新的并行全加器阵列，实现高效的卷积核映射与多核L1范数并行计算。实验结果显示，在CIFAR-10数据集上，该加速器实现90.66%的识别准确率，仅较软件模型下降1.18%，同时在133 MHz频率下达到32.31 GOPS的最大吞吐量与494.56 GOPS/W的峰值能效。
- 磁性随机存储器 /
- 加法神经网络 /
- 稀疏计算 /
- 硬件加速器 /
- 人工智能
Abstract: Objective To address the challenges of complex multiply-accumulate operations and high energy consumption in hardware implementations of Convolutional Neural Networks (CNNs), this study proposes a Processing-In-Memory (PIM) AdderNet acceleration architecture based on Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), with innovations at the circuit level. Specifically, a novel in-situ absolute difference computation circuit is designed to support L1-norm operations, replacing traditional multipliers and simplifying the data path and computational logic. By leveraging magnetic resistance state mapping, a reconfigurable full-adder unit is developed that enables single-cycle carry-chain updates and multi-mode logic switching, thereby enhancing parallel computing efficiency and energy-performance ratio. Through array-level integration and coordinated control with heterogeneous peripheral circuits, this work establishes a scalable and energy-efficient PIM-based convolutional acceleration system, providing a practical and viable paradigm for deploying deep learning hardware in resource-constrained environments. Methods To achieve energy-efficient acceleration of AdderNet in resource-constrained environments, this study proposes a circuit-level Computing-In-Memory (CIM) architecture based on STT-MRAM. The L1 norm is embedded into the memory array to enable in-situ absolute difference computation, thereby replacing conventional multiply-accumulate operations and simplifying datapath complexity. To reduce redundant operations caused by frequent zero-value interactions in AdderNet, a sparsity-aware computation strategy is implemented, which bypasses invalid operations and lowers dynamic power consumption. A reconfigurable full-adder unit is further designed using magnetoresistive state mapping, supporting single-cycle carry-chain propagation and logic mode switching. These units are integrated into a scalable parallel array structure that performs L1-norm operations efficiently. The architecture is complemented by optimized dataflow control and heterogeneous peripheral circuits, forming a complete low-power AdderNet accelerator. Simulation and hardware-level validations confirm the accuracy, throughput, and energy efficiency of the proposed system under realistic workloads. Results and Discussions Simulation results confirm the effectiveness and efficiency of the proposed MRAM-based AdderNet hardware accelerator under realistic inference workloads. The fabricated full-adder unit supports in-memory computation with dual-mode configurability for both sum and carry operations (Fig. 2, Fig. 3). The proposed 1-bit full adder produces correct logical outputs in both modes, with timing waveforms validating reliable switching behavior under a 40 nm CMOS process (Fig. 7, Fig. 8). The parallel array structure, which integrates multiple MRAM-based full-adder units, enables efficient L1-norm-based convolution through element-wise absolute difference (Fig. 4) and maps standard convolution kernels into a format compatible with the proposed architecture (Fig. 5b). Device-level Monte Carlo simulations reveal tightly distributed resistance states, with coefficients of variation of low-resistance and high-resistance states of approximately 1.1% (CVLRS) and 1.2% (CVHRS), respectively, and a resistance window of ～5349 Ω, ensuring accurate bit-level distinction (Fig. 6). The MRAM device also exhibits robust noise margins (NM ≈ 50.5), confirming its suitability for logic-in-memory operations. On the CIFAR-10 dataset, the accelerator achieves a classification accuracy of 90.66%, with only a 1.18% reduction compared with the floating-point software baseline (Fig. 9, Fig. 10). The final design achieves a peak throughput of 32.31 GOPS and a peak energy efficiency of 494.56 GOPS/W at 133 MHz, exceeding several state-of-the-art designs (Table 2). Conclusions To address the high computational complexity and energy consumption of traditional convolutional multiply-accumulate operations, this study proposes an MRAM-based AdderNet hardware accelerator that incorporates L1-norm computation and sparsity optimization strategies. At the circuit level, an in-situ absolute difference computation method based on STT-MRAM is introduced, together with a magnetic resistance state-mapped full-adder circuit that enables fast and configurable carry and sum computations. Building on these units, a scalable parallel full-adder array is constructed to replace multiplications with lightweight additions, and the complete accelerator is implemented with integrated peripheral circuits. Simulation results validate the proposed design. On the same benchmark dataset, the accelerator achieves an accuracy of 90.66% through circuit–algorithm co-optimization, with accuracy degradation limited to 1.18% compared with the software reference model. Although the training process shows periodic local oscillations, the overall convergence trend follows an exponential decay pattern. The architecture ultimately achieves a peak throughput of 32.31 GOPS and a peak energy efficiency of 494.56 GOPS/W at 133 MHz, exceeding conventional approaches in both performance and energy efficiency.
- Magnetoresistive Random Access Memory (MRAM) /
- AdderNet /
- Sparse computation /
- Hardware accelerator /
- Artificial intelligence

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图 1 STT-MRAM器件及其连接结构图

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图 2 基于STT-MRAM的全加器单元

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图 3 STT-MRAM全加器单元计算过程

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图 4 基于STT-MRAM的全加器阵列结构

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图 5 AdderNet算法的硬件架构及实现

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图 6 STT-MRAM阻态分布图

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图 7 进位Z_i+1计算时序波形图

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图 8 和位S计算时序波形图

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图 9 AdderNet的准确率与损失变化曲线

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图 10 加法器读电路的蒙特卡罗仿真

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图 11 与基准模型的混淆矩阵对比

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表 1 多层感知机操作数统计

层别	总操作数	“0”操作数	占比(%)
输入层-隐藏层	1003250000	868548048	86.57
隐藏层-输出层	12800000	6795030	53.08
输入层-输出层	1016320000	875613078	86.16

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表 2 与相关文献比较结果

	i5-1235U CPU^[14]	i7-12700H CPU^[14]	i5-1235U iGPU^[14]	i7-12700H iGPU^[14]	ICCAD 2022^[15]	TCAS-I 2024^[13]	TCAS-I 2025^[16]	本文
工艺(nm)	10	10	10	10	N/A	65	N/A	40
电压(V)	1.1-1.3	1.1-1.3	0.9-1.1	0.9-1.1	12(FPGA)	1.2	12(FPGA)	0.6-1.1
单元结构	N/A	N/A	N/A	N/A	LUT	2T1M	LUT	3T3M
频率(MHz)	4400	4700	1200	1400	200	117	200	133
位宽(bit)	8	8	8	8	8	8	6	8
功耗(mW)	5500	11500	1200	1650	1695	63.82	381	65.33
网络模型	ResNet-50	ResNet-50	ResNet-50	ResNet-50	ResNet-20	VGG-8	ResNet-20	ResNet-20
数据集	N/A	N/A	N/A	N/A	CIFAR-10	CIFAR-10	CIFAR-10	CIFAR-10
准确率(%)	N/A	N/A	N/A	N/A	89.9%	93.72%	90.52%	90.66%
最大吞吐量 (GOPS)	151.18	424	200.32	360.49	214.6	20.93	12.08/kLUT	32.31
能效 (GOPS/W)	27.48	2.6	166.9	218.48	126.6	246.68	562.5	494.56

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