芯粒集成芯片架构-封装协同设计

卢美璇; 许浩博; 王颖; 王梦迪; 韩银和

doi:10.11999/JEIT250626

芯粒集成芯片架构-封装协同设计

doi: 10.11999/JEIT250626 cstr: 32379.14.JEIT250626

卢美璇^{1, 2},
许浩博^{1, 2},
王颖^{1, 2},
王梦迪^{1, 2},
韩银和^{1, 2, ,}

1.
中国科学院计算技术研究所处理器芯片全国重点实验室北京 100190
2.
中国科学院计算技术研究所智能计算机研究中心北京 100190

基金项目: 国家自然科学基金(62025404, 62495104)

详细信息

作者简介:
卢美璇：女，博士生，研究方向为芯粒集成芯片设计

许浩博：男，副研究员，研究方向为计算机系统结构，专用处理器芯片

王颖：男，研究员，研究方向为专用处理器体系结构，集成芯片系统

王梦迪：女，助理研究员，研究方向为领域专用加速器架构设计，芯粒集成

韩银和：男，研究员，研究方向为计算机体系结构和芯片，智能机器人，智能硬件，数据计算芯片和计算系统

通讯作者:
韩银和　yinhes@ict.ac.cn

中图分类号: TN4
计量
- 文章访问数: 25
- HTML全文浏览量: 12
- PDF下载量: 4
- 被引次数: 0
出版历程
- 收稿日期: 2025-07-03
- 修回日期: 2025-09-14
- 网络出版日期: 2025-09-16

Co-design of Architecture and Packaging in Chiplet

LU Meixuan^{1, 2},
XU Haobo^{1, 2},
WANG Ying^{1, 2},
WANG Mengdi^{1, 2},
HAN Yinhe^{1, 2
, ,}

1.
SKLP, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
2.
Research Center for Intelligent Computing Systems, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China

Funds: The National Natural Science Foundation of China (62025404, 62495104)

摘要

摘要: 芯粒集成技术凭借封装集成的可扩展性，成为后摩尔时代算力拓展的有效途径。然而，芯粒集成芯片架构与封装的紧密耦合导致复杂的多目标权衡问题，同时体积集成密度的提高加剧了可靠性挑战，仅依靠封装层面设计难以解决，传统架构与封装分离的设计范式失效，架构-封装协同设计成为保障芯粒集成芯片性能与可靠性的必要手段。该工作总结芯粒集成驱动的新兴架构特征，梳理芯粒集成芯片架构与封装的紧密耦合关系，阐明协同设计的必要性；理清架构层与封装层核心设计要素对系统关键指标的影响机制，在此基础上定义架构层和封装层协同界面；最后结合已有工作提出架构-封装协同设计的关键组成和协同方法。
- 芯粒 /
- 协同设计 /
- 架构 /
- 封装
Abstract: Significance Chiplet technology, enabled by advanced packaging techniques, integrates multiple chiplets into a single package to form a larger-scale chip system. This approach breaks through the “Area Wall” faced by traditional processes and has become a critical path for improving computing performance in the post-Moore era. The design flexibility afforded by packaging-level integration has created a new design paradigm that drives iterative advances in computing and integration architectures. In traditional monolithic chip design, architecture and packaging are relatively independent stages. By contrast, the ability to integrate chiplets fabricated in different processes and the scalability of chiplet technology greatly expand the design space but also increase design complexity. At the same time, the higher transistor density per unit volume intensifies multi-physics coupling effects, including thermal, mechanical, and electrical interactions. Therefore, traditional methods that rely solely on packaging design to address performance degradation and reliability issues are no longer sufficient for chiplet-based systems. Instead, architecture and packaging in chiplet design must be co-designed in a coordinated manner. Progress This work addresses the critical issues of architecture–packaging co-design in the context of chiplet systems. It reviews architectural design and co-optimization efforts, demonstrates the necessity of co-design, and proposes co-design optimization methodologies. First, it summarizes architectural characteristics and development trends driven by advanced packaging technologies. These technologies are categorized into 2D, 2.5D, 3D, and 3.5D integration according to chiplet arrangement and interconnection technologies, each leading to substantial architectural differences. A detailed comparison of packaging technologies is provided, outlining the architectural features and co-design considerations associated with each. The necessity of co-design is then clarified from the perspective of the profound effect of packaging technologies on performance and reliability. The increased integration density per unit volume in chiplet-based circuits introduces serious reliability challenges, including complex multi-physics coupling effects such as thermal, mechanical, and electrical interactions. Multiple research studies on chiplet reliability are cited, highlighting the severity of thermal, mechanical, and electrical problems arising from these couplings. Unlike traditional monolithic chip designs, reliability issues in chiplet-integrated circuits cannot be resolved through standalone packaging-level design. Separate design of architecture and packaging introduces performance risks and leads to unpredictable design and manufacturing timelines and costs. Therefore, co-design of architecture and packaging is a necessary trend for the advancement of chiplet-based circuits. Finally, by reviewing existing cross-layer co-optimization efforts, an architecture–packaging co-optimization methodology is proposed to provide guidance for design optimization. Key design factors and evaluation metrics at both the architectural and packaging levels are summarized, and the interfaces for cross-layer co-design are clarified. The co-design interface consists of two components: design factors and evaluation metrics. Adjustments to any design factor within the design space affect multiple evaluation metrics, which in turn drive the convergence of the design space. Two key components are summarized for each design layer: (1) the definition of the design parameter space and exploration methods, and (2) the selection of evaluation metrics together with evaluation models and methodologies. The co-design process is outlined in eight key steps, illustrated by prior works. Existing architecture–packaging co-design methods are reviewed, and design workflows are categorized and characterized. Conclusions Driven by the evolution of chiplet technology and objectives such as performance and cost, chiplet-integrated circuit architectures have developed characteristics that differentiate them from traditional monolithic designs. The strong coupling between architecture and packaging layers has substantially increased design complexity, while higher integration density has introduced intricate multi-physics interactions, elevating reliability risks. The traditional design paradigm, in which architecture and packaging are developed independently, now faces challenges including performance degradation, unpredictable verification timelines, and uncontrollable costs. Co-design has therefore emerged as a critical solution. Establishing cross-layer collaborative methods and making trade-offs among multidimensional objectives are essential. By defining the design spaces for both architecture and packaging, formulating efficient exploration strategies, and applying system- and packaging-level evaluation methods, it becomes possible to rapidly and accurately identify optimal design solutions. Architecture–packaging co-design enables performance, reliability, and other objectives to be optimized synergistically at the early stages of chiplet-integrated circuit design with minimal cost. This approach maximizes the benefits of high integration density while mitigating risks in chip design and manufacturing. Prospects Architecture–packaging co-design represents the future paradigm for chiplet design. Current co-design approaches remain limited in applicability: methods that rely on detailed models such as RTL and netlists, together with EDA tools, are unsuitable for early-stage chip development, whereas abstract modeling techniques may neglect critical design issues and introduce substantial inaccuracies. Future co-design methodologies must adapt to different stages of the design process and support the iterative advancement of both computing architectures and integration architectures.
- Chiplet /
- Co-design /
- Architecture /
- Packaging

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图 1 芯粒集成芯片“DI-DA”设计模式

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图 2 芯粒集成技术和架构演变

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图 3 2D(a,b)及2.5D(c)芯粒集成芯片及架构示意图

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图 4 3D芯粒集成芯片及架构示意图

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图 5 3.5D芯粒集成芯片及架构示意图

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图 5 3.5D芯粒集成芯片及架构示意图

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图 6 芯粒集成芯片热力电耦合示意图

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表 1 芯粒集成技术对比与典型芯片

集成方式	特点	主要参数				典型芯片
集成方式	特点	线距 (μm)	凸块间距 (μm)	功耗 (pJ/bit)	归一化成本	典型芯片
2D	有机基板互连。成本低，可靠性高，面积扩展性好；互连密度低	～10	～100	～1.7	1	AMD EPYC^TM, Ryzen^TM ^[4], Nvidia Simba ^[11]
2.5D	硅等中介层互连。互连密度较高；面积受限，成本高，可靠性问题	<4	～50	～0.5	1.5～(>3)^[9]	Instinct MI200 series^[5], Intel FGPA^[15], 华为Kunpeng 920^[16], Intel Meteor Lake^[17], Intel Sapphire Rapids(SPR)^[18], Occamy^[19], Manticore^[20], Centaur^[21], AMD RadeonTM R9 Fury X^[28]
3D	垂直堆叠，硅通孔互连。互连密度高，延时、功耗低；成本高，可靠性问题显著	<2	～40	～0.15	>3^[9,26,27]	IntAct^[14], HBM^[25](商用芯片常见^[29–31]), Intel Lakefield^[32], SHINSAI^[33], Lu等人^[34], 华为 Ascend910^[35], AMD V-Cache^[36], Niu等人^[37], Samsung HBM2-PIM^[38]
3.5D	2.5D和3D结合。水平垂直互连协同设计，灵活性强；成本高，可靠性问题显著	<1	～40	<0.1	>3^[42]	Intel PVC^[43], AMD InstinctTM MI300 series ^[41,44]

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表 2 典型架构封装协同设计工作设计空间探索方法总结

协同方法组成	分类	细分类型或使用范围	典型工作(及算法)
设计空间描述	参数和功能模型	-	文献[56,58,62,64,66,68,69]
设计空间描述	详细设计描述文件	-	文献[51,57,63,67]
空间探索方法	有限设计点	架构层	文献[55,62,56,64,66,68]
	有限设计点	封装层	文献[64,68]
	迭代优化	架构层功能级分解组合	文献[58,69](启发式)，文献[56](数学建模法)
		架构层网表级分解组合	文献[51,57,67](启发式)，文献[63](数学建模法)
		封装层	文献[51,56,58,62,63,69](启发式)，文献[57,62,66,67](数学建模法)
评估指标	可靠性考量	热	文献[56,62,66]
		力	文献[57,64,66,63]
		电	文献[55,66–68]
	无可靠性考量	-	文献[58,69]
评估方法	解析模型	系统级性能、面积、功耗、成本等	文献[56–58,62,64,69]
	解析模型	封装层时序、温度、应力	文献[57–58,62]
	模拟模型	系统级性能、面积、功耗、成本等	文献[56,57,62–64,66,67,69]
	模拟模型	封装层时序、温度	文献[51,56,62,63,66–68]

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