3D IC封装技术中硅通孔研究进展综述

张芊帆; 何茜; 田雨; 丰光银

doi:10.11999/JEIT250377

3D IC封装技术中硅通孔研究进展综述

doi: 10.11999/JEIT250377 cstr: 32379.14.JEIT250377

华南理工大学微电子学院广州 511442

基金项目: 国家自然科学基金(U24B20163, 62474069)

详细信息

作者简介:
张芊帆：女，博士生，研究方向为3D-IC多物理场协同优化

何茜：女，硕士生，研究方向为3D-IC多物理场协同优化

田雨：男，硕士生，研究方向为谐波平衡分析预处理器的设计

丰光银：男，副教授，博士生导师，研究方向为毫米波收发前端芯片、高能效收发机架构、3D-IC多物理场协同优化

通讯作者:
丰光银　gyfeng88@scut.edu.cn

中图分类号: TN43
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- 被引次数: 0
出版历程
- 收稿日期: 2025-05-07
- 修回日期: 2025-08-18
- 网络出版日期: 2025-08-27

Review of Research Progress on TSV Technology in 3D IC Packaging

School of Microelectronics, South China University of Technology, Guangzhou 511442, China

Funds: The National Natural Science Foundation of China (U24B20163, 62474069)

摘要

摘要: 三维集成电路(3D IC)以其低延迟和高密度等优势，成为后摩尔时期的重要研究方向之一。其中硅通孔(TSV)作为3D IC中层间互连的关键技术，相关热、电、信号问题已有了广泛的研究。为更好地了解TSV技术的原理及研究现状，该文概述了近年来TSV技术在3D IC设计中的研究进展。首先，针对TSV热问题，综述了3D IC的热建模方法和TSV的热管理策略。其次，针对电源完整性问题，介绍了布局优化、背面供电网络(BPDN)技术等解决方案。之后，针对信号完整性问题，阐述了电磁屏蔽、应用低介电常数材料、新型互连等方法。最后，对TSV目前仍存在的局限性进行了总结，并在此基础上重点展望了多物理场协同优化、纳米级TSV(nTSV)与背面供电网络集成设计、新型材料与TSV阵列以及智能优化方法在未来的发展空间。
- 三维集成电路 /
- 硅通孔 /
- 热管理 /
- 电源完整性 /
- 信号完整性
Abstract: Significance Three-Dimensional Integrated Circuits (3D ICs) have emerged as a key research direction in the post-Moore era due to their advantages in low latency and high integration density. As electronic devices demand higher performance and smaller form factors, 3D ICs offer a compelling solution by vertically stacking multiple chip layers to achieve enhanced integration. A core enabler of 3D IC technology is Through-Silicon Via (TSV) technology, which facilitates high-density vertical interconnects across layers. TSVs have contributed significantly to performance improvements in 3D ICs but also pose challenges in thermal management, power integrity, and signal integrity, all of which can affect device reliability and operational stability. Addressing these challenges is essential for the continued advancement of 3D IC systems. This review outlines recent research on TSV technology, with an emphasis on thermal, electrical, and signal integrity issues, as well as current strategies for mitigating these limitations. Progress This review systematically summarizes the progress in TSV technology, focusing on the following areas: Thermal Management: Thermal dissipation is a critical concern in 3D ICs due to elevated power densities resulting from multilayer stacking. While TSVs improve interconnect performance, they can also introduce vertical heat flow paths that lead to localized overheating and reduced reliability. To manage this, various thermal modeling approaches—such as Finite Element Analysis (FEA) and thermal stacking simulations—have been developed to predict temperature distributions and optimize thermal performance. These models inform the layout of TSVs and guide the incorporation of Thermal TSVs (TTSVs) to enhance heat dissipation. Researchers have also explored the use of high-thermal-conductivity materials, such as carbon nanotubes and graphene, to improve thermal pathways. Optimizing TSV density and employing multi-layer thermal redistribution techniques have further advanced thermal management, contributing to better device performance and longer operational lifetimes. Power Integrity: Power integrity is a major design constraint in 3D ICs, given the complex power delivery networks required in stacked architectures. TSVs, acting as vertical power conduits, can introduce issues such as voltage drops, electromigration, and power noise. Several approaches have been proposed to address these issues. Layout optimization—particularly through uniform TSV distribution and the integration of Backside Power Delivery Networks (BPDNs)—helps reduce power delivery path lengths and mitigate voltage loss. Dynamic Voltage and Frequency Scaling (DVFS) is also employed to adapt power usage under varying workloads, particularly in high-performance computing environments. Additional methods include the use of Decoupling Capacitors (DECAPs) and Fully Integrated Voltage Regulators (FIVRs), which help suppress power noise and maintain stability across multiple voltage domains. Signal Integrity: TSV-based interconnects must maintain signal integrity at increasingly high frequencies, but parasitic inductance and capacitance inherent to TSVs can degrade signal quality through reflection, crosstalk, and delay mismatch. These effects become especially pronounced in high-density, high-speed interconnect architectures. To address this, electromagnetic shielding—using grounded TSVs and metallic isolation structures—has been shown to reduce crosstalk and enhance signal fidelity. The use of low-dielectric constant (low-k) materials further minimizes parasitic capacitance and improves signal propagation speed. Differential TSV designs and advanced interconnect architectures have also been proposed to reduce interference and enhance signal integrity. These improvements are essential for achieving reliable high-speed data transmission in storage and processing applications. Conclusions While TSV technology has advanced substantially in addressing the thermal, power, and signal integrity challenges of 3D ICs, several limitations persist. These include scalability constraints, power delivery reliability under high-density integration, and diminished signal transmission quality at high frequencies. These challenges highlight the need for continued innovation in TSV design and integration to meet the demands of next-generation 3D IC systems. Several promising research directions are emerging. First, there is a growing need for higher-precision multiphysics coupling models. As 3D ICs progress toward large-scale heterogeneous integration, high-speed data communication, and extreme energy efficiency, more accurate modeling of the thermal, electrical, and signal interactions associated with TSVs is required. This calls for enhanced integration of multiphysics simulations into the Electronic Design Automation (EDA) workflow to enable co-simulation across electrical, thermal, and signal domains. Second, co-optimization of BPDNs and nano-TSVs (nTSVs) is becoming increasingly important. As chip dimensions decrease and stacking complexity grows, traditional front-side power delivery approaches no longer meet the required power densities. Improved BPDN strategies, in conjunction with nTSV integration, will support higher stacking capability and improved energy efficiency. Third, the exploration of new materials and TSV array structures offers additional opportunities. Carbon-based nanomaterials, used as TSV fillers or liners, can alleviate thermal expansion mismatch and improve resistance to electromigration. Incorporating air gaps or low-k dielectrics as insulating liners can reduce parasitic capacitance and enhance high-speed signal performance. Meanwhile, novel TSV array architectures can increase interconnect density and improve redundancy and fault tolerance. Finally, the adoption of AI-driven TSV optimization holds considerable promise. TSV layout design currently depends heavily on manual heuristics. The application of artificial intelligence to automate TSV placement and power network distribution can significantly reduce design time and accelerate the transition toward more intelligent 3D integration design paradigms.
- Three-Dimensional Integrated Circuit (3D IC) /
- Through-Silicon Via (TSV) /
- Thermal management /
- Power integrity /
- Signal integrity

HTML全文

图 1 TSV结构示意图

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图 2 加载TSV的DRAM封装图

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图 3 具有NCTE材料的TSV结构示意图^[34]

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图 4 RDL结构^[37]

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图 5 差异化TSV结构及八边形TSV阵列示意图

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图 6 两种PEQ设计图^[54]

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图 7 无凸点封装方式图

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表 1 不同TSV散热方案的性能优劣与适用范围

方案名称	参考文献	主要优势	主要劣势	适用场景
热再分布和热硅通孔组成的冷却系统	[28]	可以实现高效散热，工艺兼容性强	垂直散热依赖TTSV密度，横向散热受TRDL影响，热耦合效应未完全解决	移动设备与物联网芯片、射频与光电集成
碳材料基TSV	[29]	具有超高导热系数，能显著提升垂直散热效率，降低芯片温度，在高频与高温环境下更稳定	材料制备与集成难度大，成本高。界面热阻可能削弱整体散热效果	高性能计算与AI芯片、航空航天与汽车电子
调整TSV参数	[31] [32] [33]	降低TSV周围热应力，减少热耦合，节省芯片面积，系统性解决热问题	增加制造复杂性，提高成本，需进一步考虑电性能与热性能的权衡	高功耗3D IC、对热应力敏感的器件
具有NCTE材料的TSV结构	[34]	具有高效应力补偿，减小禁布区，提高芯片集成密度，不影响导热性能	电阻率较高，仅在特定温度范围内有效，且材料制备困难，成本较高	高频通信与射频器件、高密度存储器
TTSV与微流冷却混合散热	[35] [36]	TSV改善纵向导热，微通道强化横向散热，实现高效散热	增加功耗和复杂度，制造成本高，具有流体泄漏风险	高性能计算芯片、功耗分布不均的芯片

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表 2 功耗控制与电源完整性硬件解决方案

方案名称	参考文献	主要优势	主要劣势	适用场景
分布式PDNTSV 布局	[13]	可显著降低供电路径阻抗，减少电源压降，延长器件寿命并提升能效	Bank平面面积增加约30%，布线与时序收敛复杂度提高	高带宽 3D-DRAM、HMC
基于网格结构的 RDL 设计	[37]	网格结构RDL可提升电流承载能力，在TSV数量相同条件下降低IR-drop	需新增网格金属，工艺成本和布线阻塞增加	TSV数量受限或分布不均的高电流异构3D-SoC/2.5D 封装
主动去耦 +FIVR 分层稳压	[38]	抑制71.1%衬底与 TSV 耦合引起的电源噪声且功耗开销仅1.11%	片上面积占用大；设计复杂	多层异构 TSV3D-IC和其他高电流、多电压域的 3DSoC
埋置式电源轨-BPDN	[39]	降低IR-drop，释放前端布线资源，改善功率密度	需背面深刻蚀与绝缘处理，热-机械失配待优化	高并行移动SoC、AINPU
背供过孔-BPDN	[40]	去掉顶层粗电源金属，缩短供电路径，兼顾工艺微缩与性能	晶圆减薄与密集nTSV良率挑战大，背面测试链尚不成熟	高性能CPU/GPU、数据中心加速器
直接背面接触	[41]	供电阻抗较另两种背面供电方案最小，抑制IR-drop与瞬态噪声，潜在性能最佳	需求极薄硅片与亚纳米级对准，工艺窗口窄，仅实验验证	超高频数字IP

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