铁电基的存算一体组合优化求解器

钱煜; 杨泽禹; 王然然; 蔡嘉豪; 李超; 黄庆荣; 樊凌雁; 李云龙; 卓成; 尹勋钊

doi:10.11999/JEIT250369

铁电基的存算一体组合优化求解器

doi: 10.11999/JEIT250369 cstr: 32379.14.JEIT250369

钱煜¹,
杨泽禹¹,
王然然³,
蔡嘉豪¹,
李超¹,
黄庆荣¹,
樊凌雁²,
李云龙³,
卓成^{3, 4},
尹勋钊^{1, 4, ,}

1.
浙江大学信息与电子工程学院杭州 310058
2.
杭州电子科技大学微电子研究院杭州 310018
3.
浙江大学集成电路学院杭州 310058
4.
浙江省协同传感与自主无人系统重点实验室杭州 310058

基金项目: 长三角科技创新共同体联合攻关项目(2024CSJZN0500)，国家自然科学基金(624B2126, W2412034, 92164203)，中德联合基金(M-0612)

详细信息

作者简介:
钱煜：男，博士生，研究方向为存算一体跨层次设计优化，组合优化求解器

杨泽禹：男，博士生，研究方向为面向神经网络加速的存算一体电路设计优化

王然然：女，博士生，研究方向为存算一体器件电路设计优化

蔡嘉豪：男，博士生，研究方向为存算一体电路架构设计优化

李超：男，博士生，研究方向为存算一体电路算法协同设计优化

黄庆荣：男，博士生，研究方向为存算一体电路架构设计优化

樊凌雁：女，研究员，研究方向为数据存储，高速接口集成电路设计

李云龙：男，教授，研究方向为先进CMOS芯片工艺与可靠性，芯片异构集成(芯粒)工艺与可靠性，硅基特殊成像器件工艺集成

卓成：男，教授，研究方向为设计自动化，低功耗芯片设计，人工智能算法及硬件

尹勋钊：男，研究员，研究方向为人工智能，存算一体，新型计算专用芯片设计，软硬件跨层协同设计优化，组合优化求解器

通讯作者:
尹勋钊　xzyin1@zju.edu.cn

中图分类号: TP333.5
计量
- 文章访问数: 20
- HTML全文浏览量: 12
- PDF下载量: 0
- 被引次数: 0
出版历程
- 收稿日期: 2025-05-06
- 修回日期: 2025-08-28
- 网络出版日期: 2025-09-02

Ferroelectric FET-based Compute-in-Memory Solver for Combinatorial Optimization Problems

1.
College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310058, China
2.
Microelectronics Research Institute, Hangzhou Dianzi University, Hangzhou 310018, China
3.
College of Integrated Circuits, Zhejiang University 310058, China
4.
Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province, Hangzhou 310058, China

Funds: Yangtze River Delta Science and Technology Innovation Community Joint Fundamental Research Project (2024CSJZN0500), The National Natural Science Foundation of China (624B2126, W2412034, 92164203), SGC Cooperation Project (M-0612)

摘要

摘要: 组合优化问题在诸多领域应用广泛，大多属于非确定多项式时间难题，基于冯·诺依曼架构的传统数字计算机难以满足其极高计算复杂度的需求。具有阈值电压可编程特性和多端口输入结构的铁电晶体管(FeFET)为高效求解组合优化问题提供了新的机遇。基于FeFET的存算一体架构具有能效高、延时低等特点，同时支持对向量-矩阵及向量-矩阵-向量乘法等复杂算子的加速，非常适合求解组合优化问题。该文回顾了FeFET的器件特性，介绍了组合优化问题的基本求解过程，并进一步探讨了近年来面向等式约束、不等式约束和纳什均衡场景下基于FeFET的存算一体组合优化求解器工作。最后，该文从多个方面分析并展望了基于FeFET的存算一体组合优化求解器的前景与挑战。
- 铁电晶体管 /
- 存算一体 /
- 组合优化
Abstract: Significance Combinatorial optimization problems (COPs) are ubiquitous, profoundly impacting diverse fields from logistics and finance to advanced AI and drug discovery. At their core, these problems demand identifying the absolute best solution from an often unfathomably vast set of possibilities. The vast majority of COPs are classified as NP-hard problems, representing one of the most significant computational challenges in computer science. Traditional digital computers, operating on the von Neumann architecture, face immense difficulties in solving COPs; as problem scales expand, required computational resources, particularly latency, increase exponentially. Given these limitations, there's an urgent need to explore novel architectures for efficiently solving COPs, a pursuit with both significant theoretical importance and profound practical implications for tackling complex, resource-intensive real-world problems. Addressing these challenges, researchers have actively explored various novel hardware-based combinatorial optimization solutions, often transforming COPs into Ising models or Quadratic Unconstrained Binary Optimization (QUBO) problems for hardware implementation. Broadly, existing approaches fall into two categories: digital Application-Specific Integrated Circuit (ASIC) annealers, which suffer from data movement bottlenecks, and dynamical system solvers, which leverage physical dynamics but often demand high device parameter precision, struggle with cross-chip scalability, and may find it difficult to integrate Ising model self-interaction terms. Beyond these, other non-traditional methods like quantum computing (e.g., D-Wave's quantum annealers requiring cryogenic cooling and having limited connectivity) and certain optical computing approaches (e.g., relying on extremely long optical fibers) exist. While offering unique physical advantages, they generally face substantial challenges in integrating with mature silicon-based Very Large Scale Integration (VLSI) circuits. Consequently, despite a range of novel hardware solutions, their individual limitations highlight the critical need for new combinatorial optimization solvers that offer higher integration, better scalability, superior energy efficiency, and broader problem type support. Process Ferroelectric field-effect transistors (FeFETs), with their unique threshold voltage programmability and multi-port input structure, are opening exciting new avenues for efficiently solving combinatorial optimization problems (COPs). The FeFET-based compute-in-memory (CiM) architecture is particularly well-suited for these challenges, boasting high energy efficiency, low latency, and the inherent ability to accelerate complex operations like vector-matrix and vector-matrix-vector multiplications. Recent research has seen numerous works proposing FeFET-based CiM COP solvers to tackle a diverse range of problems, including those with equality constraints, inequality constraints, and Nash equilibrium scenarios. The overall solving process for these innovative FeFET-based CiM solutions generally involves four key steps: (1) Problem transformation, where the COP is converted into a hardware-friendly objective function, often by encoding equality constraints, introducing slack variables or penalty methods for inequality constraints, or formulating coupled optimization problems for Nash equilibrium scenarios; (2) Following transformation, the objective function undergoes a crucial compression process. This is specifically achieved by analyzing the simulated annealing algorithm itself, which allows for the partial activation of matrix columns, thus significantly reducing the typical computational complexity associated with fully active matrices. Furthermore, this step involves approximating and merging the exponential function components inherent in the algorithm directly into the matrix representation, thereby optimizing the function for efficient hardware implementation on the CiM array; (3) Leveraging the unique three-port and four-port structures of FeFETs, specialized CiM circuit designs are utilized to achieve high-speed acceleration of the compressed objective function. This allows for the efficient computation of a single iteration or a key part of the objective function often within a single clock cycle, significantly mitigating the von Neumann bottleneck; and (4) Finally, based on the optimized and simplified objective function, combinatorial optimization algorithms, such as simulated annealing, are simplified and applied over multiple cycles. This iterative process, efficiently accelerated by the underlying CiM hardware, aims to achieve high-quality and efficient solutions for the given problem. This structured approach highlights the adaptability and potential of FeFET-based CiM for a broad spectrum of challenging combinatorial optimization tasks. Conclusions This paper provides a comprehensive review of FeFET-based CiM solvers for solving COPs, which are prevalent across various domains and demand significant computational resources. It first outlines the device characteristics of FeFET and the fundamental process of solving COPs. The core of the paper focused on recent advancements in FeFET-based CiM solvers tailored for three specific scenarios: equality constraints, inequality constraints, and Nash equilibrium. The discussion highlighted how these architectures leverage the unique properties of FeFET to address the computational intensity of these problems. Prospects FeFET-based COP solvers show immense potential. By merging FeFET device strengths with CiM advantages, these solvers offer an efficient path to tackling highly complex optimization challenges, leading to substantial gains in speed and energy efficiency for real-world problems. However, significant challenges remain: (1) FeFET endurance is limited, restricting the number of processable problems. (2) Analog-to-digital converters (ADCs) in FeFET CiM arrays incur large area, power, and latency overheads. (3) Simulated annealing algorithms, when applied to large-scale problems, suffer from slow convergence due to increased iterations. Addressing these will be crucial for the widespread adoption and advancement of FeFET-based CiM solutions.
- Ferroelectric FET (FeFET) /
- Compute-in-Memory (CiM) /
- Combinatorial Optimization

HTML全文

图 1 FeFET器件的阈值电压可编程特性^[37,41]

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图 2 FeFET器件的多端口输入特性

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图 3 面向等式约束的存算一体组合优化求解器^[40]

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图 4 目标函数的去冗余算法

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图 5 基于FeFET的存算阵列实现目标函数计算

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图 6 面向不等式约束的存算一体组合优化求解器HyCiM^[37]

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图 7 HyCiM求解器中的存算一体不等式判断电路

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图 8 面向纳什均衡的存算一体组合优化求解器C-Nash^[38,39]

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图 9 支持小数输入的存算阵列

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