Automated Discovery of Exploitable Instruction Patterns for KASLR Circumvention
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摘要: 现代操作系统采用内核地址空间随机化(KASLR)技术来抵御内核代码重用攻击。处理器微架构侧信道能够泄漏内核代码段的页表信息,进而可以被用来绕过KASLR 保护,但是现有研究局限于MOV, CMASKMOV, PREFETCHNTA和CLDEMOTE等少数的几条指令来探测内核地址,攻击面有限。为系统评估KASLR攻击面,该文从指令多样性出发,设计一个自动化分析框架,挖掘可以绕过 KASLR 保护并暴露计算机系统安全脆弱性的指令。该框架不需要逆向微架构部件的实现细节,专注于攻击任务本身,首先将攻击流程抽象为环境准备、内存探测、微架构信息记录和差分分析的4个阶段,然后定位绕过 KASLR 保护的关键攻击代码,最后研究不同指令在替换关键代码后的攻击效果。该文分别从指令的汇编形式和字节形式出发提出两套KASLR攻击面的评估算法,互相验证和补充。实验结果表明,该文在Intel x86指令集挖掘出699条可实现KASLR绕过的汇编指令,相比现有研究依赖的6条指令,实现了KASLR脆弱性指令的跨数量级增长。此外,从字节形式出发的实验数据表明,Intel x86指令集有39个单字节操作码、121个双字节操作码和24个3字节操作码指令可以实现KASLR绕过。该文的发现不仅显著扩展了KASLR的攻击面,更为基于特征检测的防御机制带来挑战和新思路。Abstract:
Objective Kernel Address Space Layout Randomization (KASLR) remains a core defense against kernel-level exploits; however, its robustness is increasingly undermined by microarchitectural side-channel attacks that exploit specific processor instructions. Existing research has largely concentrated on isolated attack vectors, lacking a systematic evaluation of the entire x86 instruction set. This study addresses this limitation by developing an automated framework to identify and characterize KASLR-bypass instructions comprehensively, assess their attack efficacy across multiple Intel processor generations, and derive defensible instruction patterns to inform the reinforcement of current security mechanisms. Methods This study systematically addresses three core challenges in analyzing instruction-level mechanisms for bypassing KASLR. The first challenge is achieving comprehensive coverage of the x86 Instruction Set Architecture (ISA), which includes thousands of historical and modern instructions characterized by variable-length encoding and complex microarchitectural dependencies. To address this, the proposed framework combines static and dynamic analysis. Instruction semantics are extracted statically from Intel Software Developer Manuals and uops.info XML datasets. Dynamic profiling on Intel Core processors is used to verify instruction support across processor generations. Byte-level pattern matching is applied to accurately handle variable-length encodings. The second challenge concerns the generation of attack-compliant machine code that satisfies strict encoding requirements and bypasses compiler-level checks. This is achieved using a template-driven approach, which modifies a CLFLUSH-based attack prototype by replacing inline assembly instructions through pattern substitution. Memory operands are redirected to target addresses preloaded into the EDX register, with boundary values used to ensure operand validity. For nonstandard or undocumented instructions, self-modifying code techniques dynamically inject opcodes at runtime, thereby bypassing compiler restrictions and enabling broader instruction coverage. The third challenge focuses on evaluating attack effectiveness through accurate localization of kernel symbols. To this end, the framework applies a dual-verification strategy. RDTSC instructions are used to timestamp memory probes across 512 predefined address slots. Differential timing analysis identifies latency outliers (i.e., maximum and minimum values), indicating potential KASLR bypasses. Signal handlers suppress exceptions caused by access to privileged or unmapped memory regions, while debug symbol cross-referencing is used to confirm actual kernel address leakage. All generated code undergoes Monte Carlo simulation to reduce false positives and ensure statistical robustness. Results and Discussions Experiments are performed on Intel Core i7-11700K, i7-12700K, and i7- 13700 processors (Table 1 ). In the Assembly-Level Instruction Analysis (Fig. 4 ), 699 assembly instructions are identified as effective KASLR bypass vectors on the i7-11700K. Variations in support for AVX512 instruction set extensions account for differences in the attack surface, with the number of effective instructions decreasing slightly to 542 on the i7-12700K and 547 on the i7-13700 , reflecting minor microarchitectural differences. In the Byte-Level Instruction Analysis (Table 2 ), 39 one-byte, 121 two-byte, and 24 three-byte opcodes are found to bypass KASLR without relying on predefined assembly semantics. These opcodes demonstrate consistent attack efficacy across all evaluated processors, indicating similar behavioral patterns across Intel architectures. Overall, the results—supported by (Fig. 4 ,Table 2 ,Table 3 )—demonstrate two principal findings: comprehensive coverage of the x86 ISA and cross-generation consistency of effective KASLR bypass instructions. Although the current study focuses on Intel processors, the findings raise open questions regarding the vulnerability of AMD processors that share the same ISA, as well as ARM-based platforms used in Android devices and Apple M series chips. Future work is intended to extend the framework to analyze KASLR bypass vectors on non-Intel architectures. Furthermore, an automated analysis framework is proposed to assess KASLR attack efficacy through differential analysis. To enhance detection across heterogeneous architectures and instruction sets, future efforts will incorporate data preprocessing techniques to improve the scalability and precision.Conclusions KASLR remains a critical defense against kernel memory exploitation; however, its resilience is increasingly challenged by instruction-dependent microarchitectural side-channel attacks. This study presents an automated framework that systematically identifies potential KASLR-bypass instructions, quantifies their attack effectiveness across multiple Intel processor generations, and derives actionable defense signatures to address emerging threats. The findings reveal a significantly underestimated attack surface: hundreds of x86 instructions, at both the assembly and byte levels, are capable of leaking sensitive address information. The broader implications of this work are threefold: (1) Defensive Improvement: The experimental results may be directly applied to enhance signature-based detection systems. (2) Hardware–Software Co-Design: The consistent vulnerability observed across Intel microarchitectures highlights the need to redesign timing isolation mechanisms at the hardware level. (3) Methodological Contribution: The proposed dual-analysis framework offers a generalizable approach for evaluating instruction-level attack surfaces, with applicability to other contexts such as cache-based side-channel attacks. Future research will extend this methodology to alternative architectures, including ARM and RISC-V, and explore the integration of machine learning techniques. -
1 基于 CLFLUSH 指令的内存访问时间测量
输入:待探测地址集合 addr[1···512], 攻击次数 cycles 输出:内核符号地址 1: 数组初始化 count[512][cycles] ← 0,time[512] ← 0 2: for i = 1 to 512 do 3: for j = 1 to cycles do 4: start ← RDTSC() 5: for k = 1 to 1000 do6: CLFLUSH(addr[i]) 7: end for 8: end ← RDTSC() 9: count[i][j] ← (end - start) 10: end for 11: end for 12: for i = 1 to 512 do 13: /* 处理 count[i][1..cycles] 的数据 */ 14: repeat 15: 移除零值,并计算有效值的平均数 μ 16: 计算标准差 σ 17: 移除超出 (μ ± 2σ) 范围的异常值 18: until 没有新的异常值被移除 19: time[i] ← μ 20: end for 21: 找出 time[1..512] 中最小值的索引 index 22: return addr[index] 表 1 实验环境设置
处理器 微架构 微码 操作系统 内核 页表层级 i7-11700k Rocket Lake 0x63 Ubuntu 22.04 5.15.0-136-generic 4 i7-12700k Alder Lake 0x38 Ubuntu 22.04 5.15.0-135-generic 4 i7- 13700 Raptor Lake 0x12C Ubuntu 22.04 6.8.0-52-generic 4 表 2 KASLR 攻击的脆弱性机器指令实验数据(单字节)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0 add add add add add add push es pop es or or or or or or push cs 转义 1 adc adc adc adc adc adc push ss pop ss sbb sbb sbb sbb sbb sbb push ds pop ds 2 and and and and and and 前缀 daa sub sub sub sub sub sub 前缀 das 3 xor xor xor xor xor xor 前缀 aaa cmp cmp cmp cmp cmp cmp 前缀 aas 4 inc inc inc inc inc inc inc inc dec dec dec dec dec dec dec dec 5 push push push push push push push push pop pop pop pop pop pop pop pop 6 pusha popa bound arpl 前缀 前缀 前缀 前缀 push imul push imul ins ins outs outs 7 jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc 8 组 组 组 组 test test xchg xchg mov mov mov mov mov lea mov 组 9 nop xchg xchg xchg xchg xchg xchg xchg cbw cwq call fwait pushf popf sahf lahf a mov mov mov mov movs movs cmps cmps test test stos stos lods loads scas scas b mov mov mov mov mov mov mov mov mov mov mov mov mov mov mov mov c 组 组 ret ret les lds mov mov enter leave ret ret int3 int into iret d 组 组 组 组 aam aad salc xlat 组 组 组 组 组 组 组 组 e loopne loope loop jrcxz in in out out call jmp jmp jmp in in out out f 前缀 int1 前缀 前缀 hlt cmc 组 组 clc stc cli sti cld std 组 组 表 3 KASLR 攻击的脆弱性机器指令实验数据(双字节、0x0F 转义)
0 1 2 3 4 5 6 7 8 9 a b c d e f 0 组 组 lar lsl syscal clts sysret invd wbinvd 非法 prefetchw 1 vmovups vmovups vmovlps vmovlps vunpcklps vunpckhps vmovhps vmovhps prefetch nop bndldx bndstx nop nop nop nop 2 mov mov mov mov vmovaps vmovaps cvtsi2ps vmovntps cvttps2pi cvttps3pi vucomiss vcomiss 3 wrmsr rdtsc rdmsr rdpmc sysenter sysexit getsec 转义 转义 4 cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc cmovcc 5 vmovmskps vsqrtps vsqrtps vrcpps vandps vandnps vorps vxorps vaddps vmulps vcvtps2pd vcvtdq2ps vsubps vminps vdivps vmaxps 6 punpcklbw punpcklwd punpckldq packsswb pcmpgtb pcmpgtw pcmpgtd packuswb punpckhbw punpckhwd punpckhdq pqckssdw movd movq 7 pshufw 组 组 组 pcmpeqb pcmpegw pcmpeqd emms vmread vmwrite movd movq 8 jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc jcc 9 setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc setcc a push fs pop fs cpuid bt shld shld push gs pop gs rsm bts shrd shrd 组 imul b cmpxchg cmpxchg lss btr lfs lgs movzx movzx jmpe 组 组 btc bsf bsr movsx movsx c xadd xadd xcmpps movnti pinsrw pextrw vshufps 组 bswap bswap bswap bswap bswap bswap bswap bswap d psrlw psrld psrlq paddq pmullw pmovmskb psubusb psubusw pminub pand paddusb paddusw pmaxub pandn e pavgb psraw psrad pavgw pmulhuw pmulhw movntq psubsb psubsw pminsw por paddsb paddsw pmaxsw pxor f psllw pslld psllq pmuludq pmadd psadbw maskmovq psubb psubw psubd psubq psubd paddw paddd -
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